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/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Dadd-with-overflow-24.ll6 define i1 @func1(i24 signext %v1, i24 signext %v2) nounwind {
8 %t = call {i24, i1} @llvm.sadd.with.overflow.i24(i24 %v1, i24 %v2)
9 %sum = extractvalue {i24, i1} %t, 0
10 %sum32 = sext i24 %sum to i32
11 %obit = extractvalue {i24, i1} %t, 1
23 define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
25 %t = call {i24, i1} @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)
26 %sum = extractvalue {i24, i1} %t, 0
27 %sum32 = zext i24 %sum to i32
28 %obit = extractvalue {i24, i1} %t, 1
[all …]
/external/llvm/test/CodeGen/Generic/
Dadd-with-overflow-24.ll6 define i1 @func1(i24 signext %v1, i24 signext %v2) nounwind {
8 %t = call {i24, i1} @llvm.sadd.with.overflow.i24(i24 %v1, i24 %v2)
9 %sum = extractvalue {i24, i1} %t, 0
10 %sum32 = sext i24 %sum to i32
11 %obit = extractvalue {i24, i1} %t, 1
23 define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
25 %t = call {i24, i1} @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)
26 %sum = extractvalue {i24, i1} %t, 0
27 %sum32 = zext i24 %sum to i32
28 %obit = extractvalue {i24, i1} %t, 1
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dsdivrem24.ll57 %num.i24.0 = shl i32 %num, 8
58 %den.i24.0 = shl i32 %den, 8
59 %num.i24 = ashr i32 %num.i24.0, 8
60 %den.i24 = ashr i32 %den.i24.0, 8
61 %result = sdiv i32 %num.i24, %den.i24
76 %num.i24.0 = shl i32 %num, 7
77 %den.i24.0 = shl i32 %den, 7
78 %num.i24 = ashr i32 %num.i24.0, 7
79 %den.i24 = ashr i32 %den.i24.0, 7
80 %result = sdiv i32 %num.i24, %den.i24
[all …]
Dudivrem24.ll74 %num.i24.0 = shl i32 %num, 8
75 %den.i24.0 = shl i32 %den, 8
76 %num.i24 = lshr i32 %num.i24.0, 8
77 %den.i24 = lshr i32 %den.i24.0, 8
78 %result = udiv i32 %num.i24, %den.i24
92 %den.i24.0 = shl i32 %den, 8
94 %den.i24 = lshr i32 %den.i24.0, 8
95 %result = udiv i32 %num.i23, %den.i24
108 %num.i24.0 = shl i32 %num, 8
110 %num.i24 = lshr i32 %num.i24.0, 8
[all …]
Dudiv.ll139 define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
140 %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1
141 %num = load i24, i24 addrspace(1) * %in
142 %den = load i24, i24 addrspace(1) * %den_ptr
143 %result = udiv i24 %num, %den
144 %result.ext = zext i24 %result to i32
Dsdiv.ll117 define void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
118 %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1
119 %num = load i24, i24 addrspace(1) * %in
120 %den = load i24, i24 addrspace(1) * %den_ptr
121 %result = sdiv i24 %num, %den
122 %result.ext = sext i24 %result to i32
Dload-weird-sizes.ll11 define void @load_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) #0 {
12 %1 = load i24, i24 addrspace(1)* %in
13 %2 = zext i24 %1 to i32
/external/llvm/test/CodeGen/X86/
Dwiden_bitops-0.ll6 ; AND/XOR/OR i24 as v3i8
9 define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind {
21 %1 = bitcast i24 %a to <3 x i8>
22 %2 = bitcast i24 %b to <3 x i8>
24 %4 = bitcast <3 x i8> %3 to i24
25 ret i24 %4
28 define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind {
40 %1 = bitcast i24 %a to <3 x i8>
41 %2 = bitcast i24 %b to <3 x i8>
43 %4 = bitcast <3 x i8> %3 to i24
[all …]
Dpr26835.ll7 define i24 @foo(i24 %a, i24 %b) {
8 %r = urem i24 %a, %b
9 ret i24 %r
Dmasked-iv-unsafe.ll20 %indvar.i24 = and i64 %indvar, 16777215
21 %t3 = getelementptr double, double* %d, i64 %indvar.i24
48 %indvar.i24 = and i64 %indvar, 16777215
49 %t3 = getelementptr double, double* %d, i64 %indvar.i24
78 %indvar.i24 = ashr i64 %s1, 24
79 %t3 = getelementptr double, double* %d, i64 %indvar.i24
108 %indvar.i24 = ashr i64 %s1, 24
109 %t3 = getelementptr double, double* %d, i64 %indvar.i24
136 %indvar.i24 = and i64 %indvar, 16777215
137 %t3 = getelementptr double, double* %d, i64 %indvar.i24
[all …]
Dmasked-iv-safe.ll22 %indvar.i24 = and i64 %indvar, 16777215
23 %t3 = getelementptr double, double* %d, i64 %indvar.i24
55 %indvar.i24 = and i64 %indvar, 16777215
56 %t3 = getelementptr double, double* %d, i64 %indvar.i24
90 %indvar.i24 = ashr i64 %s1, 24
91 %t3 = getelementptr double, double* %d, i64 %indvar.i24
125 %indvar.i24 = ashr i64 %s1, 24
126 %t3 = getelementptr double, double* %d, i64 %indvar.i24
158 %indvar.i24 = and i64 %indvar, 16777215
159 %t3 = getelementptr double, double* %d, i64 %indvar.i24
[all …]
Dglobal-fill.ll3 @test1 = global [2 x i24] [i24 -1, i24 -1]
Dbitreverse.ll143 declare i24 @llvm.bitreverse.i24(i24) readnone
145 define i24 @test_bitreverse_i24(i24 %a) nounwind {
244 %b = call i24 @llvm.bitreverse.i24(i24 %a)
245 ret i24 %b
324 define i24 @fold_i24() {
329 %b = call i24 @llvm.bitreverse.i24(i24 4096)
330 ret i24 %b
D2011-06-03-x87chain.ll38 %x.1.copyload = load i24, i24* undef, align 1
39 %conv = sitofp i24 %x.1.copyload to float
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Dadd-overflow.ll3 %0 = type { i24, i1 } ; type %0
5 define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
7 %t = call %0 @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2) ; <%0> [#uses=1]
18 declare %0 @llvm.uadd.with.overflow.i24(i24, i24) nounwind
/external/llvm/test/Transforms/SROA/
Dbig-endian.ll6 ; We fully promote these to the i24 load or store size, resulting in just masks
24 %aiptr = bitcast [3 x i8]* %a to i24*
25 %ai = load i24, i24* %aiptr
28 ; CHECK: %[[ext2:.*]] = zext i8 0 to i24
29 ; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
30 ; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
31 ; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
33 ; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmasked-iv-unsafe.ll20 %indvar.i24 = and i64 %indvar, 16777215
21 %t3 = getelementptr double* %d, i64 %indvar.i24
48 %indvar.i24 = and i64 %indvar, 16777215
49 %t3 = getelementptr double* %d, i64 %indvar.i24
78 %indvar.i24 = ashr i64 %s1, 24
79 %t3 = getelementptr double* %d, i64 %indvar.i24
108 %indvar.i24 = ashr i64 %s1, 24
109 %t3 = getelementptr double* %d, i64 %indvar.i24
136 %indvar.i24 = and i64 %indvar, 16777215
137 %t3 = getelementptr double* %d, i64 %indvar.i24
[all …]
Dmasked-iv-safe.ll25 %indvar.i24 = and i64 %indvar, 16777215
26 %t3 = getelementptr double* %d, i64 %indvar.i24
53 %indvar.i24 = and i64 %indvar, 16777215
54 %t3 = getelementptr double* %d, i64 %indvar.i24
83 %indvar.i24 = ashr i64 %s1, 24
84 %t3 = getelementptr double* %d, i64 %indvar.i24
113 %indvar.i24 = ashr i64 %s1, 24
114 %t3 = getelementptr double* %d, i64 %indvar.i24
141 %indvar.i24 = and i64 %indvar, 16777215
142 %t3 = getelementptr double* %d, i64 %indvar.i24
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dsplit-index-tc.ll24 %1 = bitcast [3 x i8]* %IsDef.i to i24*
25 %bf.load.i = load i24, i24* %1, align 1
26 %2 = and i24 %bf.load.i, 128
30 %3 = zext i24 %2 to i32
64 %bf.load.i259 = load i24, i24* %1, align 1
/external/llvm/test/CodeGen/ARM/
D2010-09-21-OptCmpBug.ll56 br i1 undef, label %bb13.i19, label %bb.i24.i
67 bb.i24.i: ; preds = %bb.i24.i, %bb9.i
68 %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
71 br i1 %exitcond47.i, label %bb22, label %bb.i24.i
79 bb22: ; preds = %bb.i24.i, %bb5
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2010-09-21-OptCmpBug.ll56 br i1 undef, label %bb13.i19, label %bb.i24.i
67 bb.i24.i: ; preds = %bb.i24.i, %bb9.i
68 %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
71 br i1 %exitcond47.i, label %bb22, label %bb.i24.i
79 bb22: ; preds = %bb.i24.i, %bb5
/external/llvm/test/tools/llvm-nm/X86/
Dradix.s179 .type i24,@object # @i24
180 .globl i24 symbol
182 i24: label
184 .size i24, 4
/external/llvm/test/Transforms/SimplifyCFG/
DCoveredLookupTable.ll10 ; CHECK-NEXT: zext i3 %switch.tableidx to i24
11 ; CHECK-NEXT: mul i24 %switch.cast, 3
12 ; CHECK-NEXT: lshr i24 7507338, %switch.shiftamt
13 ; CHECK-NEXT: trunc i24 %switch.downshift to i3
/external/llvm/test/Transforms/InstCombine/
Dsitofp.ll127 ; CHECK: zext i24
129 define i32 @test14(i24 %A) nounwind {
130 %B = uitofp i24 %A to float
138 ; CHECK-NEXT: ret i24
139 define i24 @test15(i32 %A) nounwind {
141 %C = fptoui float %B to i24
142 ret i24 %C
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs-small-structs-byte.ll170 %.coerce = alloca { i24 }
173 %1 = bitcast { i24 }* %.coerce to i8*
176 %3 = getelementptr { i24 }, { i24 }* %.coerce, i32 0, i32 0
177 %4 = load i24, i24* %3, align 1
178 …rgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i24 inreg %4)

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