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/external/llvm/test/MC/Sparc/
Dsparc-v9-traps.s3 ! CHECK: ta %icc, %i5 ! encoding: [0x91,0xd0,0x00,0x1d]
6 ! CHECK: ta %icc, %i5 + 41 ! encoding: [0x91,0xd7,0x60,0x29]
7 ta %icc, %i5
10 ta %icc, %i5 + 41
12 ! CHECK: tn %icc, %i5 ! encoding: [0x81,0xd0,0x00,0x1d]
15 ! CHECK: tn %icc, %i5 + 41 ! encoding: [0x81,0xd7,0x60,0x29]
16 tn %icc, %i5
19 tn %icc, %i5 + 41
21 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
23 ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
[all …]
Dsparc-traps.s3 ! CHECK: ta %i5 ! encoding: [0x91,0xd0,0x00,0x1d]
6 ! CHECK: ta %i5 + 41 ! encoding: [0x91,0xd7,0x60,0x29]
7 ta %i5
10 ta %i5 + 41
12 ! CHECK: tn %i5 ! encoding: [0x81,0xd0,0x00,0x1d]
15 ! CHECK: tn %i5 + 41 ! encoding: [0x81,0xd7,0x60,0x29]
16 tn %i5
19 tn %i5 + 41
21 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
23 ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d]
[all …]
Dsparcv9-instructions.s100 ! V8-NEXT: ldx [%g2 + %i5],%fsr
101 ! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
102 ldx [%g2 + %i5],%fsr
110 ! V8-NEXT: stx %fsr,[%g2 + %i5]
111 ! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
112 stx %fsr,[%g2 + %i5]
237 ! V8-NEXT: rdpr %tpc,%i5
238 ! V9: rdpr %tpc, %i5 ! encoding: [0xbb,0x50,0x00,0x00]
239 rdpr %tpc,%i5
241 ! V8-NEXT: rdpr %tnpc,%i5
[all …]
Dsparc-nop-data.s8 xor %i5, %i5, %i5
10 xor %i5, %i5, %i5
Dsparc-special-registers.s46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/external/valgrind/none/tests/s390x/
Drxsbg.c4 #define DO_RXSBG(insn, _r1, _r2, i3, i4, i5) \ argument
9 asm volatile( insn(1,2, i3, i4, i5) \
15 …printf(#insn " r1(==%16.16lX),r2(==%16.16lX),0x" #i3 ",0x" #i4 ",0x" #i5 " = %16.16lX (cc=%d)\n", …
18 #define r1sweep(i, r2, i3, i4, i5) \ argument
20 DO_RXSBG(i, 000000000000000000ul, r2, i3, i4, i5); \
21 DO_RXSBG(i, 0x0000ffffccccaaaaul, r2, i3, i4, i5); \
22 DO_RXSBG(i, 0xfffffffffffffffful, r2, i3, i4, i5); \
25 #define r2sweep(i, i3, i4, i5) \ argument
27 r1sweep(i, 0x0000000000000000ul, i3, i4, i5); \
28 r1sweep(i, 0x5555ccccffff0000ul, i3, i4, i5); \
[all …]
/external/libcxx/test/std/iterators/stream.iterators/istreambuf.iterator/istreambuf.iterator_op!=/
Dnot_equal.pass.cpp31 std::istreambuf_iterator<char> i5(nullptr); in main() local
37 assert( (i1 != i5)); in main()
43 assert( (i2 != i5)); in main()
49 assert(!(i3 != i5)); in main()
55 assert(!(i4 != i5)); in main()
57 assert( (i5 != i1)); in main()
58 assert( (i5 != i2)); in main()
59 assert(!(i5 != i3)); in main()
60 assert(!(i5 != i4)); in main()
61 assert(!(i5 != i5)); in main()
[all …]
/external/libcxx/test/std/iterators/stream.iterators/istreambuf.iterator/istreambuf.iterator_op==/
Dequal.pass.cpp31 std::istreambuf_iterator<char> i5(nullptr); in main() local
37 assert(!(i1 == i5)); in main()
43 assert(!(i2 == i5)); in main()
49 assert( (i3 == i5)); in main()
55 assert( (i4 == i5)); in main()
57 assert(!(i5 == i1)); in main()
58 assert(!(i5 == i2)); in main()
59 assert( (i5 == i3)); in main()
60 assert( (i5 == i4)); in main()
61 assert( (i5 == i5)); in main()
[all …]
/external/libcxx/test/std/iterators/stream.iterators/istreambuf.iterator/istreambuf.iterator_equal/
Dequal.pass.cpp29 std::istreambuf_iterator<char> i5(nullptr); in main() local
35 assert(!i1.equal(i5)); in main()
41 assert(!i2.equal(i5)); in main()
47 assert( i3.equal(i5)); in main()
53 assert( i4.equal(i5)); in main()
55 assert(!i5.equal(i1)); in main()
56 assert(!i5.equal(i2)); in main()
57 assert( i5.equal(i3)); in main()
58 assert( i5.equal(i4)); in main()
59 assert( i5.equal(i5)); in main()
[all …]
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-v9.txt6 # CHECK: ta %icc, %i5
15 # CHECK: ta %icc, %i5 + 41
18 # CHECK: tn %icc, %i5
27 # CHECK: tg %icc, %i5 + 41
30 # CHECK: tle %icc, %i5
39 # CHECK: tgu %icc, %i5 + 41
42 # CHECK: tleu %icc, %i5
51 # CHECK: tpos %icc, %i5 + 41
54 # CHECK: tneg %icc, %i5
63 # CHECK: ta %xcc, %i5
[all …]
Dsparc.txt249 # CHECK: ta %i5
258 # CHECK: ta %i5 + 41
261 # CHECK: tn %i5
270 # CHECK: tg %i5 + 41
273 # CHECK: tle %i5
282 # CHECK: tgu %i5 + 41
285 # CHECK: tleu %i5
294 # CHECK: tpos %i5 + 41
297 # CHECK: tneg %i5
/external/swiftshader/third_party/LLVM/test/Transforms/IndVarSimplify/
Dloop_evaluate_5.ll7 define i32 @testcase(i5 zeroext %k) nounwind readnone {
16 %k_01 = phi i5 [ %indvar_next1, %bb2 ], [ 0, %bb.nph ] ; <i5> [#uses=2]
17 %tmp2 = zext i5 %k_01 to i32 ; <i32> [#uses=1]
19 %indvar_next1 = add i5 %k_01, 1 ; <i5> [#uses=2]
23 %phitmp = icmp eq i5 %indvar_next1, -16 ; <i1> [#uses=1]
DiterationCount_zext_or_trunc.ll7 define i32 @testcase(i5 zeroext %k) {
13 %indvar_next1 = add i5 %k_0, 1 ; <i5> [#uses=1]
17 %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; <i5> [#uses=2]
19 %tmp2 = zext i5 %k_0 to i32 ; <i32> [#uses=1]
/external/llvm/test/Transforms/IndVarSimplify/
Dloop_evaluate_5.ll7 define i32 @testcase(i5 zeroext %k) nounwind readnone {
16 %k_01 = phi i5 [ %indvar_next1, %bb2 ], [ 0, %bb.nph ] ; <i5> [#uses=2]
17 %tmp2 = zext i5 %k_01 to i32 ; <i32> [#uses=1]
19 %indvar_next1 = add i5 %k_01, 1 ; <i5> [#uses=2]
23 %phitmp = icmp eq i5 %indvar_next1, -16 ; <i1> [#uses=1]
DiterationCount_zext_or_trunc.ll7 define i32 @testcase(i5 zeroext %k) {
13 %indvar_next1 = add i5 %k_0, 1 ; <i5> [#uses=1]
17 %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; <i5> [#uses=2]
19 %tmp2 = zext i5 %k_0 to i32 ; <i32> [#uses=1]
/external/libcxx/test/std/iterators/stream.iterators/istream.iterator/istream.iterator.ops/
Dequal.pass.cpp34 std::istream_iterator<int> i5; in main() local
39 assert(i1 != i5); in main()
44 assert(i2 != i5); in main()
48 assert(i3 != i5); in main()
51 assert(i4 == i5); in main()
/external/clang/test/CodeGen/
Darm64-arguments.c297 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
350 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
405 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
460 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
517 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/mesa3d/src/mesa/sparc/
Dsparc_clip.S80 LDPTR [%i1 + V4F_START], %i5
132 st %g0, [%i5 + 0x00] ! LSU
135 st %g0, [%i5 + 0x04] ! LSU
137 st %g0, [%i5 + 0x08] ! LSU
139 st %f4, [%i5 + 0x0c] ! LSU Group
144 st %f0, [%i5 + 0x00] ! LSU Group
146 st %f1, [%i5 + 0x04] ! LSU Group
148 st %f2, [%i5 + 0x08] ! LSU Group
149 st %f8, [%i5 + 0x0c] ! LSU Group
150 3: add %i5, 0x10, %i5 ! IEU1
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dcode_placement_eh.ll14 br i1 undef, label %bb18.i5.i, label %bb15
16 .noexc6.i.i: ; preds = %bb18.i5.i
18 to label %bb18.i5.i unwind label %lpad.i.i ; <float> [#uses=0]
20 bb18.i5.i: ; preds = %.noexc6.i.i, %bb51.i
24 lpad.i.i: ; preds = %bb18.i5.i, %.noexc6.i.i
/external/llvm/test/CodeGen/X86/
Dcode_placement_eh.ll14 br i1 undef, label %bb18.i5.i, label %bb15
16 .noexc6.i.i: ; preds = %bb18.i5.i
18 to label %bb18.i5.i unwind label %lpad.i.i ; <float> [#uses=0]
20 bb18.i5.i: ; preds = %.noexc6.i.i, %bb51.i
24 lpad.i.i: ; preds = %bb18.i5.i, %.noexc6.i.i
/external/llvm/test/CodeGen/SPARC/
D64spill.ll13 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
24 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
35 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
47 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
58 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
69 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
80 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
91 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
102 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
113 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
/external/llvm/test/CodeGen/PowerPC/
Dcr-spills.ll80 %cond.i5.i1516 = select i1 %cmp.i4.i1515, i32 %cond.i.i1514, i32 %1
83 %sub301 = sub nsw i32 %cond.i5.i1516, %conv300
99 %cond.i5.i1508 = select i1 %cmp.i4.i1507, i32 %cond.i.i1506, i32 %1
100 %sub329 = sub nsw i32 %cond.i5.i1508, 0
108 %cond.i5.i1504 = select i1 %cmp.i4.i1503, i32 %cond.i.i1502, i32 %1
112 %sub343 = sub nsw i32 %cond.i5.i1504, %conv342
127 %cond.i5.i1500 = select i1 %cmp.i4.i1499, i32 %cond.i.i1498, i32 %1
131 %sub357 = sub nsw i32 %cond.i5.i1500, %conv356
146 %cond.i5.i1496 = select i1 %cmp.i4.i1495, i32 %cond.i.i1494, i32 %1
150 %sub371 = sub nsw i32 %cond.i5.i1496, %conv370
[all …]
/external/llvm/test/tools/llvm-nm/X86/
Dradix.s46 .type i5,@object # @i5
47 .globl i5 symbol
49 i5: label
51 .size i5, 4
/external/lzma/CPP/Common/
DMyCom.h212 #define MY_UNKNOWN_IMP5(i1, i2, i3, i4, i5) MY_UNKNOWN_IMP_SPEC( \ argument
218 MY_QUERYINTERFACE_ENTRY(i5) \
221 #define MY_UNKNOWN_IMP6(i1, i2, i3, i4, i5, i6) MY_UNKNOWN_IMP_SPEC( \ argument
227 MY_QUERYINTERFACE_ENTRY(i5) \
231 #define MY_UNKNOWN_IMP7(i1, i2, i3, i4, i5, i6, i7) MY_UNKNOWN_IMP_SPEC( \ argument
237 MY_QUERYINTERFACE_ENTRY(i5) \
/external/llvm/test/Assembler/
Duselistorder.ll10 @glob1 = global i5 7
11 @glob2 = global i5 7
12 @glob3 = global i5 7
55 uselistorder i5 7, { 1, 0, 2 }

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