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/external/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dweird-type-accesses.ll14 declare void @use_v2i9(<2 x i9>)
178 ; CHECK: store i9 3
179 ; CHECK: store i9 -5
180 define void @merge_store_2_constants_i9(i9 addrspace(1)* %out) #0 {
181 %out.gep.1 = getelementptr i9, i9 addrspace(1)* %out, i32 1
182 store i9 3, i9 addrspace(1)* %out.gep.1
183 store i9 -5, i9 addrspace(1)* %out
188 ; CHECK: load <2 x i9>
189 ; CHECK: load <2 x i9>
190 define void @merge_load_2_constants_v2i9(<2 x i9> addrspace(1)* %out) #0 {
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
61 ; CHECK-NEXT: ret i9 %a
63 %and = and i9 %b, 496 ; 0x1f0
64 %shl = shl i9 %a, %and
65 ret i9 %shl
71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) {
73 ; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8
74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
77 %and = and i9 %b, 504 ; 0x1f8
[all …]
/external/swiftshader/third_party/LLVM/test/Analysis/ScalarEvolution/
Dsext-iv-1.ll17 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
18 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
40 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
41 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
63 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
64 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
86 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
87 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
Dsext-iv-0.ll20 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
23 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
/external/llvm/test/Analysis/ScalarEvolution/
Dsext-iv-1.ll24 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
47 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
70 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
71 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
93 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
94 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
Dsext-iv-0.ll20 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
23 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2009-07-20-DAGCombineBug.ll14 bb3.i9: ; preds = %bb3.i17
17 bb1.i15: ; preds = %bb3.i9
20 bb2.i16: ; preds = %bb3.i9
24 br i1 false, label %bb3.i9, label %bsR.exit18
D2007-02-16-BranchFold.ll31 br label %bb.i9.i.i932.ce
56 bb.i9.i.i932.ce: ; preds = %newFuncRoot
63 …%tmp5.i9.i = call i32 (%struct.FILE*, i8*, ...)* @fprintf( %struct.FILE* %tmp3.i8.i, i8* getelemen…
68 NodeBlock5: ; preds = %bb.i9.i.i932.ce
/external/llvm/test/CodeGen/X86/
D2009-07-20-DAGCombineBug.ll14 bb3.i9: ; preds = %bb3.i17
17 bb1.i15: ; preds = %bb3.i9
20 bb2.i16: ; preds = %bb3.i9
24 br i1 false, label %bb3.i9, label %bsR.exit18
D2007-02-16-BranchFold.ll31 br label %bb.i9.i.i932.ce
56 bb.i9.i.i932.ce: ; preds = %newFuncRoot
63 …%tmp5.i9.i = call i32 (%struct.FILE*, i8*, ...) @fprintf( %struct.FILE* %tmp3.i8.i, i8* getelement…
68 NodeBlock5: ; preds = %bb.i9.i.i932.ce
Ddagcombine-unsafe-math.ll51 %vecext1.i9.i153 = extractelement <4 x float> %mul.i.i151, i32 0
52 %add.i10.i154 = fadd float %vecext1.i9.i153, %vecext.i8.i152
/external/clang/test/CodeGen/
Darm64-arguments.c298 int i9, s38_no_align s1, s38_no_align s2) { in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
351 int i9, s39_with_align s1, s39_with_align s2) { in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
406 int i9, s40_no_align s1, s40_no_align s2) { in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
461 int i9, s41_with_align s1, s41_with_align s2) { in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
518 int i9, s42_no_align s1, s42_no_align s2) { in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/llvm/test/tools/llvm-nm/X86/
Dradix.s74 .type i9,@object # @i9
75 .globl i9 symbol
77 i9: label
79 .size i9, 4
/external/swiftshader/third_party/LLVM/test/Assembler/
D2004-06-07-VerifierBug.ll8 %tmp.4.i9 = getelementptr i32* null, i32 %tmp.5.i10 ; <i32*> [#uses=1]
9 %tmp.5.i10 = load i32* %tmp.4.i9 ; <i32> [#uses=1]
/external/llvm/test/Assembler/
D2004-06-07-VerifierBug.ll9 %tmp.4.i9 = getelementptr i32, i32* null, i32 %tmp.5.i10 ; <i32*> [#uses=1]
10 %tmp.5.i10 = load i32, i32* %tmp.4.i9 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/ARM/
D2009-06-02-ISelCrash.ll38 bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer
42 br i1 undef, label %bb2.i9.i, label %bb1.i.i
44 bb2.i9.i: ; preds = %bb1.i.i
47 bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2009-06-02-ISelCrash.ll38 bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer
42 br i1 undef, label %bb2.i9.i, label %bb1.i.i
44 bb2.i9.i: ; preds = %bb1.i.i
47 bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
/external/llvm/test/Transforms/InstCombine/
Dapint-sub.ll73 define i1 @test11(i9 %A, i9 %B) {
74 %C = sub i9 %A, %B ; <i9> [#uses=1]
75 %cD = icmp ne i9 %C, 0 ; <i1> [#uses=1]
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dapint-sub.ll73 define i1 @test11(i9 %A, i9 %B) {
74 %C = sub i9 %A, %B ; <i9> [#uses=1]
75 %cD = icmp ne i9 %C, 0 ; <i1> [#uses=1]
/external/llvm/test/CodeGen/AMDGPU/
Dsi-vector-hang.ll31 %arrayidx2.i9.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 5
32 %10 = load i8, i8 addrspace(1)* %arrayidx2.i9.i, align 1
55 %arrayidx2.i9.i8 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 5
56 %26 = load i8, i8 addrspace(1)* %arrayidx2.i9.i8, align 1
58 %arrayidx6.i11.i9 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 6
59 %28 = load i8, i8 addrspace(1)* %arrayidx6.i11.i9, align 1
/external/libvpx/libvpx/vp8/common/x86/
Dloopfilter_block_sse2_x86_64.asm183 %define i9 [spp + 8 * stride]
224 movdqa xmm4, i9
232 movdqa xmm8, i9
239 movdqa i9, xmm8
342 %define i9 [rsp + 144]
531 movdqa i9, xmm12
563 movdqa xmm4, i9
571 movdqa xmm4, i9
578 movdqa i9, xmm4
603 punpcklbw xmm0, i9 ; 80 90
[all …]
/external/llvm/test/Transforms/GlobalOpt/
D2008-01-03-Crash.ll10 br i1 false, label %cond_next20.i, label %cond_true.i9
12 cond_true.i9: ; preds = %entry
/external/swiftshader/third_party/LLVM/test/Transforms/GlobalOpt/
D2008-01-03-Crash.ll10 br i1 false, label %cond_next20.i, label %cond_true.i9
12 cond_true.i9: ; preds = %entry
/external/llvm/test/Instrumentation/MemorySanitizer/
Dwith-call-type-size.ll33 define <4 x i32> @test9(<4 x i32> %vec, i9 %idx, i32 %x) sanitize_memory {
34 %vec1 = insertelement <4 x i32> %vec, i32 %x, i9 %idx
38 ; CHECK: %[[A:.*]] = zext i9 {{.*}} to i16
/external/llvm/test/CodeGen/PowerPC/
Dstdux-constuse.ll20 %i9 = getelementptr i64, i64* %i6, i64 100000
24 store i64 %add, i64* %i9, align 32

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