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Searched refs:isDef (Results 1 – 25 of 185) sorted by relevance

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/external/clang/test/Index/skip-parsed-bodies/
Dcompile_commands.json23 …]: kind: c++-instance-method | name: method_decl | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0
24 …]: kind: c++-instance-method | name: method_def1 | {{.*}} | isRedecl: 0 | isDef: 1 | isContainer: 1
26 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0
27 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 1 | isDef: 1 | isContainer: 1
31 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo1 | {{.*}} | isRedecl: 0 | isDef: 1 | …
39 …]: kind: c++-instance-method | name: method_decl | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0
40 …]: kind: c++-instance-method | name: method_def1 | {{.*}} | isRedecl: 0 | isDef: 1 | isContainer: …
41 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0
45 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo1 | {{.*}} | isRedecl: 0 | isDef: 1 | …
47 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo2 | {{.*}} | isRedecl: 0 | isDef: 1 | …
[all …]
/external/llvm/lib/CodeGen/
DImplicitNullChecks.cpp207 if (MO.isDef()) { in rememberInstruction()
266 assert((!MO.isDef() || RegDefs.count(MO.getReg())) && in isSafeToHoist()
268 return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI; in isSafeToHoist()
282 if (MO.isDef()) in isSafeToHoist()
436 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in analyzeBlockForNullChecks()
542 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
552 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in rewriteNullChecks()
DLiveRangeCalc.cpp62 if (!MO.isDef() && !MO.readsReg()) in calculate()
93 if (MO.isDef()) in calculate()
100 if (MO.isDef()) in calculate()
107 if (MO.isDef() && !LI.hasSubRanges()) in calculate()
188 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses()
196 if (MO.isDef()) in extendToUses()
DMachineInstrBundle.cpp141 if (MO.isDef()) { in finalizeBundle()
280 if (MO.isDef()) in analyzeVirtReg()
285 if (MO.isDef()) in analyzeVirtReg()
327 } else if (MO.isDef()) { in analyzePhysReg()
DMachineInstr.cpp177 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister() argument
195 IsDef = isDef; in ChangeToRegister()
225 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
268 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
319 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || in print()
323 if (isDef()) { in print()
1004 if (MO.isDef()) { in isIdenticalTo()
1058 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
1349 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1402 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
[all …]
DMachineLICM.cpp386 if (!MO.isDef()) { in ProcessMI()
505 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
531 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
719 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
814 if (MO.isDef()) in calcRegisterCost()
937 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
1006 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1101 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist()
1254 if (MO.isReg() && MO.isDef() && in EliminateCSE()
1346 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
DRenameIndependentSubregs.cpp180 if (!MO.isDef() && !MO.readsReg()) in findComponents()
190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents()
219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands()
334 if (!MO.isDef()) in computeMainRangesFixFlags()
DDeadMachineInstructionElim.cpp79 if (MO.isReg() && MO.isDef()) { in isDead()
145 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
DVirtRegMap.cpp411 if (MO.readsReg() && (MO.isDef() || MO.isKill())) in rewrite()
414 if (MO.isDef()) { in rewrite()
429 assert(MO.isDef()); in rewrite()
437 if (MO.isDef()) in rewrite()
DCriticalAntiDepBreaker.cpp261 if (!MO.isDef()) continue; in ScanInstruction()
341 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs()
352 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
358 if (RefOper->isDef()) in isNewRegClobberedByRefs()
607 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
DLivePhysRegs.cpp49 if (!O->isDef()) in stepBackward()
82 if (O->isDef()) { in stepForward()
DLiveRangeEdit.cpp171 if (MO.isDef()) { in foldAsLoad()
289 else if (MOI->isDef()) in eliminateDeadDef()
299 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || in eliminateDeadDef()
304 if (MOI->isDef()) { in eliminateDeadDef()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineInstr.cpp69 if (*Head && (*Head)->isDef()) in AddRegOperandToRegInfo()
155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister() argument
176 IsDef = isDef; in ChangeToRegister()
196 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
242 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || in print()
246 if (isDef()) { in print()
759 if (MO.isDef()) { in isIdenticalTo()
951 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
995 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) in isRegTiedToUseOperand()
1024 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); in isRegTiedToUseOperand()
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DDeadMachineInstructionElim.cpp71 if (MO.isReg() && MO.isDef()) { in isDead()
136 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction()
165 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
DMachineLICM.cpp413 if (!MO.isDef()) { in ProcessMI()
516 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
546 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
713 if (MO.isDef()) in InitRegPressure()
743 if (MO.isDef()) in UpdateRegPressure()
915 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
970 if (MO.isDef()) { in UpdateBackTraceRegPressure()
1031 if (MO.isDef()) { in IsProfitableToHoist()
1079 if (!MO.isReg() || !MO.isDef()) in IsProfitableToHoist()
1192 if (MO.isReg() && MO.isDef() && in EliminateCSE()
[all …]
DLiveRangeEdit.cpp90 if (!MO.isReg() || !MO.getReg() || MO.isDef()) in allUsesAvailableAt()
174 if (MO.isDef()) { in foldAsLoad()
256 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) || in eliminateDeadDefs()
261 if (MOI->isDef()) { in eliminateDeadDefs()
DPeepholeOptimizer.cpp283 if (MO.isDef()) in OptimizeBitcastInstr()
305 if (!MO.isReg() || MO.isDef()) in OptimizeBitcastInstr()
310 if (!MO.isDef()) { in OptimizeBitcastInstr()
378 if (!MO.isReg() || MO.isDef()) in FoldImmediate()
DProcessImplicitDefs.cpp143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef()) in runOnMachineFunction()
170 if (MO.isDef()) { in runOnMachineFunction()
191 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction()
DRegisterScavenging.cpp171 assert(MO.isDef()); in forward()
214 assert(MO.isDef()); in forward()
292 if (MO.isDef()) in findSurvivorReg()
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h282 bool isDef() const { in isDef() function
580 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
606 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
613 assert(!(isDead && !isDef) && "Dead flag on non-def");
614 assert(!(isKill && isDef) && "Kill flag on def");
616 Op.IsDef = isDef;
/external/llvm/lib/Target/AArch64/
DAArch64DeadRegisterDefinitionsPass.cpp72 if (MO.isReg() && MO.isDef()) in implicitlyDefinesOverlappingReg()
104 if (MO.isReg() && MO.isDead() && MO.isDef()) { in processMachineBasicBlock()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineOperand.h236 bool isDef() const { in isDef() function
463 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
489 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
496 Op.IsDef = isDef;
/external/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp412 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
519 if (Op.isReg() && Op.isDef() && DefRegs.count(Op)) in updateDeadsInRange()
654 assert(MD.isDef()); in split()
726 if (!Op.isReg() || !Op.isDef()) in isPredicable()
763 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
810 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver()
879 if (!MO.isReg() || !MO.isDef()) in predicateAt()
935 assert(!Op.isDef() && "Not expecting a def"); in renameInRange()
1015 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate()
/external/llvm/lib/CodeGen/GlobalISel/
DRegBankSelect.cpp121 if (MO.isDef()) in repairReg()
179 if (MO.isDef()) in getRepairCost()
242 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit()
245 if (!MO.isDef()) { in tryAvoidingSplit()
269 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit()
583 bool Before = !MO.isDef(); in RepairingPlacement()
/external/llvm/lib/Target/AMDGPU/
DSIInsertWaits.cpp231 if (Op.isDef()) in isOpRelevant()
346 if (Op.isDef()) in pushInstruction()
475 if (Op.isDef()) { in handleOperands()
507 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0) in handleSendMsg()

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