Searched refs:isR (Results 1 – 2 of 2) sorted by relevance
| /external/valgrind/VEX/priv/ |
| D | host_generic_reg_alloc2.c | 697 const Bool isR = (rRead & jMask) != 0; in doRegisterAllocation() local
705 if (isW && !isR) { in doRegisterAllocation()
712 } else if (!isW && isR) { in doRegisterAllocation()
725 vassert(isR && isW); in doRegisterAllocation()
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| D | guest_arm64_toIR.c | 7916 Bool isR, UInt size, IRTemp vN, IRTemp vM ) in math_SQDMULH() argument
7927 if (isR) { in math_SQDMULH()
9635 Bool isR = opcode == BITS5(0,1,0,1,0); in dis_AdvSIMD_scalar_three_same() local
9636 IROp op = isR ? (isU ? mkVecRSHU(size) : mkVecRSHS(size)) in dis_AdvSIMD_scalar_three_same()
9641 const HChar* nm = isR ? (isU ? "urshl" : "srshl") in dis_AdvSIMD_scalar_three_same()
9655 Bool isR = opcode == BITS5(0,1,0,1,1); in dis_AdvSIMD_scalar_three_same() local
9656 IROp op = isR ? (isU ? mkVecQANDUQRSH(size) : mkVecQANDSQRSH(size)) in dis_AdvSIMD_scalar_three_same()
9677 const HChar* nm = isR ? (isU ? "uqrshl" : "sqrshl") in dis_AdvSIMD_scalar_three_same()
9723 Bool isR = bitU == 1; in dis_AdvSIMD_scalar_three_same() local
9729 math_SQDMULH(&res, &sat1q, &sat1n, isR, size, vN, vM); in dis_AdvSIMD_scalar_three_same()
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