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Searched refs:kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-a32-shadd16.h292 const Inputs kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0[] = { variable
8896 ARRAY_SIZE(kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0),
8897 kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0,
Dsimulator-cond-rd-rn-rm-t32-shadd16.h292 const Inputs kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0[] = { variable
8896 ARRAY_SIZE(kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0),
8897 kOutputs_Shadd16_RdIsRnIsRm_al_r0_r0_r0,