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Searched refs:kOutputs_Shadd16_RdIsRn_al_r5_r5_r6 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-a32-shadd16.h1764 const Inputs kOutputs_Shadd16_RdIsRn_al_r5_r5_r6[] = { variable
8972 ARRAY_SIZE(kOutputs_Shadd16_RdIsRn_al_r5_r5_r6),
8973 kOutputs_Shadd16_RdIsRn_al_r5_r5_r6,
Dsimulator-cond-rd-rn-rm-t32-shadd16.h1764 const Inputs kOutputs_Shadd16_RdIsRn_al_r5_r5_r6[] = { variable
8972 ARRAY_SIZE(kOutputs_Shadd16_RdIsRn_al_r5_r5_r6),
8973 kOutputs_Shadd16_RdIsRn_al_r5_r5_r6,