Searched refs:ldrex (Results 1 – 25 of 38) sorted by relevance
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24 ; CHECK: ldrex29 ; CHECK: ldrex34 ; CHECK: ldrex39 ; CHECK: ldrex44 ; CHECK: ldrex49 ; CHECK: ldrex54 ; CHECK: ldrex59 ; CHECK: ldrex65 ; CHECK: ldrex70 ; CHECK: ldrex[all …]
41 %val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr)51 %val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr)57 ; CHECK: ldrex r0, [r0]59 %val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)63 declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly64 declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly65 declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly111 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020)113 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]118 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024)[all …]
29 ; CHECK: ldrex37 ; CHECK: ldrex45 ; CHECK: ldrex53 ; CHECK: ldrex61 ; CHECK: ldrex69 ; CHECK: ldrex77 ; CHECK: ldrex85 ; CHECK: ldrex94 ; CHECK: ldrex102 ; CHECK: ldrex[all …]
6 ; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]16 ; CHECK: ldrex [[LOADED]], [r0]82 ; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]92 ; CHECK: ldrex [[LOADED]], [r0]
6 ; CHECK: ldrex16 ; CHECK: ldrex
9 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]39 ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
5 ; CHECK-T1-NOT: ldrex51 ; CHECK: ldrex [[OLD:r[0-9]+]], [r0]
55 ; CHECK: ldrex
66 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]544 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]641 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]754 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]1109 ; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]1414 ; CHECK: ldrex
8 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)26 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)45 ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)62 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)81 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)129 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)148 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)168 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)188 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)208 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)[all …]
9 ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)48 ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)88 ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)123 ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
8 ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
26 ldrex r0, [r12] ; \
64 ldrex r1, [r2, #4] label
1053 ldrex r1, [r4]1054 ldrex r8, [r4, #0]1055 ldrex r2, [sp, #128]1060 @ CHECK: ldrex r1, [r4] @ encoding: [0x54,0xe8,0x00,0x1f]1061 @ CHECK: ldrex r8, [r4] @ encoding: [0x54,0xe8,0x00,0x8f]1062 @ CHECK: ldrex r2, [sp, #128] @ encoding: [0x5d,0xe8,0x20,0x2f]
47 …%asmtmp.i.i.i = tail call %0 asm sideeffect "\0A0:\09ldrex $1, [$2]\0A\09orr $1, $1, $3\0A\09strex…
164 # CHECK: ldrex r8, [r2]
709 # CHECK: ldrex r1, [r4]710 # CHECK: ldrex r8, [r4]711 # CHECK: ldrex r2, [sp, #128]
629 # CHECK: ldrex r1, [r4]630 # CHECK: ldrex r8, [r4]631 # CHECK: ldrex r2, [sp, #128]
750 ldrex r1, [r4]751 ldrex r8, [r4, #0]752 ldrex r2, [sp, #128]757 @ CHECK: ldrex r1, [r4] @ encoding: [0x54,0xe8,0x00,0x1f]758 @ CHECK: ldrex r8, [r4] @ encoding: [0x54,0xe8,0x00,0x8f]759 @ CHECK: ldrex r2, [sp, #128] @ encoding: [0x5d,0xe8,0x20,0x2f]
765 ldrex r1, [r7]770 @ CHECK: ldrex r1, [r7] @ encoding: [0x9f,0x1f,0x97,0xe1]
1003 void ldrex(Register dst, Register src, Condition cond = al);
1835 the exclusive monitor in between an ``ldrex`` type operation and its paired1841 Also, loads and stores may be implicit in code written between the ``ldrex`` and