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Searched refs:ldrexd (Results 1 – 25 of 42) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dldstrexd.ll7 ; CHECK: ldrexd
10 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
11 %0 = extractvalue %0 %ldrexd, 1
12 %1 = extractvalue %0 %ldrexd, 0
31 declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
Datomic-64bit.ll6 ; CHECK: ldrexd r2, r3
20 ; CHECK: ldrexd r2, r3
34 ; CHECK: ldrexd r2, r3
48 ; CHECK: ldrexd r2, r3
62 ; CHECK: ldrexd r2, r3
76 ; CHECK: ldrexd r2, r3
88 ; CHECK: ldrexd r2, r3
101 ; FIXME: Should compile to a single ldrexd
104 ; CHECK: ldrexd r2, r3
121 ; CHECK: ldrexd r2, r3
/external/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll9 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
15 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
Dgpr-paired-spill.ll6 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
7 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
8 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
9 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
Datomic-64bit.ll9 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
38 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
67 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
79 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
96 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
108 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
125 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
137 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
[all …]
Dldstrex.ll9 ; CHECK: ldrexd
12 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
13 %0 = extractvalue %0 %ldrexd, 1
14 %1 = extractvalue %0 %ldrexd, 0
33 declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
DPR15053.ll5 declare { i32, i32 } @llvm.arm.ldrexd(i8*) nounwind readonly
9 %0 = tail call { i32, i32 } @llvm.arm.ldrexd(i8* undef) nounwind
Dldstrex-m.ll6 ; CHECK-NOT: ldrexd
22 ; CHECK-NOT: ldrexd
Dinlineasm-64bit.ll6 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
8 …%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A te…
49 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
52 …%1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $…
Dcmpxchg-O0.ll70 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
88 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
107 ; CHECK: ldrexd
Darm-modifier.ll64 ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
65 …%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nou…
Datomic-ops-v8.ll89 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
377 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
473 ; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
780 ; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
1140 ; CHECK: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
/external/llvm/test/MC/Disassembler/ARM/
Darm-LDREXD-reencoding.txt9 # CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
10 # CHECK: ldrexd r12, sp, [r1] @ encoding: [0x9f,0xcf,0xb1,0xe1]
11 # CHECK: ldrexd r12, sp, [r3] @ encoding: [0x9f,0xcf,0xb3,0xe1]
12 # CHECK: ldrexd r8, r9, [sp] @ encoding: [0x9f,0x8f,0xbd,0xe1]
13 # CHECK: ldrexd r12, sp, [lr] @ encoding: [0x9f,0xcf,0xbe,0xe1]
Dinvalid-thumbv7-xfail.txt5 # Undefined encodings for ldrexd/strexd
8 # FIXME: "ldrexd r8, r8, [r2]"
Dthumb-tests.txt167 # CHECK: ldrexd r8, r9, [r2]
/external/llvm/test/MC/ARM/
Dthumb2-ldrexd-strexd.s7 ldrexd r0, r1, [r2]
10 @ CHECK: ldrexd r0, r1, [r2] @ encoding: [0xd2,0xe8,0x7f,0x01]
Dthumbv8m.s74 ldrexd r0, r1, [r2] label
Ddiagnostics.s300 @ Out of order Rt/Rt2 operands for ldrexd/strexd
301 ldrexd r4, r3, [r8]
305 @ CHECK-ERRORS: ldrexd r4, r3, [r8]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll9 %ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p)
10 %0 = extractvalue %0 %ldrexd, 1
11 %1 = extractvalue %0 %ldrexd, 0
148 %ldrexd = tail call %0 @llvm.aarch64.ldaxp(i8* %p)
149 %0 = extractvalue %0 %ldrexd, 1
150 %1 = extractvalue %0 %ldrexd, 0
/external/compiler-rt/lib/builtins/arm/
Dsync-ops.h43 ldrexd r0, r1, [r12] ; \
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Ddiagnostics.s231 @ Out of order Rt/Rt2 operands for ldrexd/strexd
232 ldrexd r4, r3, [r8]
236 @ CHECK-ERRORS: ldrexd r4, r3, [r8]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb-tests.txt167 # CHECK: ldrexd r8, r9, [r2]
/external/llvm/test/Transforms/AtomicExpand/ARM/
Datomic-expansion-v7.ll102 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
366 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
Datomic-expansion-v8.ll204 ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td347 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.

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