Searched refs:lrvr (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/test/CodeGen/SystemZ/ |
| D | bswap-01.ll | 11 ; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
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| D | bswap-04.ll | 93 ; CHECK: lrvr [[REG:%r[0-5]]], %r3
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| D | bswap-07.ll | 93 ; CHECK: lrvr [[REG:%r[0-5]]], %r3
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| D | bswap-06.ll | 94 ; CHECK: lrvr %r2, [[REG]]
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| D | bswap-02.ll | 94 ; CHECK: lrvr %r2, [[REG]]
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| /external/swiftshader/third_party/LLVM/test/CodeGen/SystemZ/ |
| D | 11-BSwap.ll | 15 ; CHECK: lrvr [[R1:%r.]], %r2
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| /external/v8/src/compiler/s390/ |
| D | code-generator-s390.cc | 1994 __ lrvr(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
1998 __ lrvr(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
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| /external/llvm/test/MC/SystemZ/ |
| D | insn-good.s | 6983 #CHECK: lrvr %r0, %r0 # encoding: [0xb9,0x1f,0x00,0x00]
6984 #CHECK: lrvr %r0, %r15 # encoding: [0xb9,0x1f,0x00,0x0f]
6985 #CHECK: lrvr %r15, %r0 # encoding: [0xb9,0x1f,0x00,0xf0]
6986 #CHECK: lrvr %r7, %r8 # encoding: [0xb9,0x1f,0x00,0x78]
6987 #CHECK: lrvr %r15, %r15 # encoding: [0xb9,0x1f,0x00,0xff]
6989 lrvr %r0,%r0
6990 lrvr %r0,%r15
6991 lrvr %r15,%r0
6992 lrvr %r7,%r8
6993 lrvr %r15,%r15
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| /external/v8/src/s390/ |
| D | assembler-s390.h | 794 RRE_FORM(lrvr);
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| D | assembler-s390.cc | 1434 RRE_FORM_EMIT(lrvr, LRVR) in RX_FORM_EMIT()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 494 "lrvr\t{$dst, $src}",
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| /external/llvm/test/MC/Disassembler/SystemZ/ |
| D | insns.txt | 5551 # CHECK: lrvr %r0, %r0
5554 # CHECK: lrvr %r0, %r15
5557 # CHECK: lrvr %r15, %r0
5560 # CHECK: lrvr %r7, %r8
5563 # CHECK: lrvr %r15, %r15
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| /external/valgrind/docs/internals/ |
| D | s390-opcodes.csv | 500 lrvr,"load reversed 32",implemented,
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