Searched refs:lsrs (Results 1 – 25 of 61) sorted by relevance
123
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 377 lsrs r1, r3, #1
378 lsrs r1, r3, #32
379 lsrs r4, #20
380 lsrs r4, r4, #20
381 lsrs r2, r4, #20
383 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
384 @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
385 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
386 @ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
387 @ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
[all …]
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| D | thumb_rewrites.s | 74 lsrs r0, r0, r1
75 @ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40]
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-shifter.ll | 59 ; A8: lsrs r1, r2
63 ; SWIFT-NOT: lsrs
99 ; SWIFT: lsrs
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| D | bfi.ll | 22 ; CHECK: lsrs r1, r1, #7
33 ; CHECK: lsrs {{.*}}, #7
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| D | thumb2-lsr.ll | 5 ; CHECK: lsrs r0, r0, #13
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| D | thumb2-lsr2.ll | 5 ; CHECK: lsrs r0, r1
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| D | thumb2-lsr3.ll | 5 ; CHECK: lsrs.w r1, r1, #1
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| D | float-intrinsics-float.ll | 119 ; NONE: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
121 ; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
123 ; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
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| D | float-intrinsics-double.ll | 115 ; SP: lsrs r2, r3, #31
126 ; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
128 ; VFP: lsrs [[REG:r[0-9]+]], r3, #31
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| /external/llvm/test/CodeGen/ARM/Windows/ |
| D | vla.ll | 18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
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| D | alloca.ll | 21 ; CHECK: lsrs r4, [[R0]], #2
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| D | bfi.ll | 22 ; CHECK: lsrs r1, r1, #7
33 ; CHECK: lsrs {{.*}}, #7
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| D | thumb2-lsr.ll | 5 ; CHECK: lsrs r0, r0, #13
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| D | thumb2-lsr2.ll | 5 ; CHECK: lsrs r0, r1
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| D | thumb2-lsr3.ll | 5 ; CHECK: lsrs.w r1, r1, #1
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| D | thumb2-sxt_rot.ll | 22 ; CHECK: lsrs r0, r0, #8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 334 lsrs r1, r3, #1
335 lsrs r1, r3, #32
337 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
338 @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
344 lsrs r2, r6
346 @ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40]
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| /external/llvm/test/CodeGen/ARM/ |
| D | long_shift.ll | 6 ; CHECK-LE: lsrs r3, r3, #1
10 ; CHECK-BE: lsrs r2, r2, #1
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| D | thumb2-size-opt.ll | 71 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
80 ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| D | ispositive.ll | 6 ; CHECK: lsrs r0, r0, #31
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| /external/llvm/test/CodeGen/Thumb/ |
| D | ispositive.ll | 6 ; CHECK: lsrs r0, r0, #31
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| /external/compiler-rt/lib/builtins/arm/ |
| D | clzsi2.S | 51 lsrs r2, r0, shift; \
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| D | clzdi2.S | 72 lsrs r2, r0, shift; \
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 240 # CHECK: lsrs r1, r3, #1
241 # CHECK: lsrs r1, r3, #32
250 # CHECK: lsrs r2, r6
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 255 # CHECK: lsrs r1, r3, #1
256 # CHECK: lsrs r1, r3, #32
265 # CHECK: lsrs r2, r6
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123