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Searched refs:lwl (Results 1 – 25 of 73) sorted by relevance

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/external/v8/src/mips64/
Dcodegen-mips64.cc92 __ lwl(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
251 __ lwl(v1, in CreateMemCopyUint8Function()
257 __ lwl(v1, MemOperand(a1)); in CreateMemCopyUint8Function()
311 __ lwl(a4, in CreateMemCopyUint8Function()
313 __ lwl(a5, in CreateMemCopyUint8Function()
315 __ lwl(a6, in CreateMemCopyUint8Function()
317 __ lwl(a7, in CreateMemCopyUint8Function()
319 __ lwl(t0, in CreateMemCopyUint8Function()
321 __ lwl(t1, in CreateMemCopyUint8Function()
323 __ lwl(t2, in CreateMemCopyUint8Function()
[all …]
/external/v8/src/mips/
Dcodegen-mips.cc92 __ lwl(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
250 __ lwl(v1, in CreateMemCopyUint8Function()
256 __ lwl(v1, MemOperand(a1)); in CreateMemCopyUint8Function()
310 __ lwl(t0, in CreateMemCopyUint8Function()
312 __ lwl(t1, in CreateMemCopyUint8Function()
314 __ lwl(t2, in CreateMemCopyUint8Function()
316 __ lwl(t3, in CreateMemCopyUint8Function()
318 __ lwl(t4, in CreateMemCopyUint8Function()
320 __ lwl(t5, in CreateMemCopyUint8Function()
322 __ lwl(t6, in CreateMemCopyUint8Function()
[all …]
/external/valgrind/none/tests/mips64/
Dload_store.stdout.exp-LE16513 lwl :: offset: 0x0, out: 0x0
16514 lwl :: offset: 0x1, out: 0x0
16515 lwl :: offset: 0x2, out: 0x0
16516 lwl :: offset: 0x3, out: 0x0
16517 lwl :: offset: 0x4, out: 0x0
16518 lwl :: offset: 0x5, out: 0x0
16519 lwl :: offset: 0x6, out: 0x0
16520 lwl :: offset: 0x7, out: 0x0
16521 lwl :: offset: 0x8, out: 0x6e000000
16522 lwl :: offset: 0x9, out: 0x3b6e0000
[all …]
Dload_store.stdout.exp-BE16513 lwl :: offset: 0x0, out: 0x0
16514 lwl :: offset: 0x1, out: 0x0
16515 lwl :: offset: 0x2, out: 0x0
16516 lwl :: offset: 0x3, out: 0x0
16517 lwl :: offset: 0x4, out: 0x0
16518 lwl :: offset: 0x5, out: 0x0
16519 lwl :: offset: 0x6, out: 0x0
16520 lwl :: offset: 0x7, out: 0x0
16521 lwl :: offset: 0x8, out: 0x9823b6e
16522 lwl :: offset: 0x9, out: 0xffffffff823b6e00
[all …]
Dunaligned_load_store.stdout.exp-BE1 PRE lwl
9 POST lwl
Dunaligned_load_store.stdout.exp-LE1 PRE lwl
9 POST lwl
/external/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll28 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
31 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
37 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
40 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
80 ; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]])
82 ; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]])
85 ; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]])
87 ; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]])
111 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
114 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
[all …]
Dunalignedload.ll43 ; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]])
53 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]])
/external/llvm/test/MC/Mips/
Dmips-expansions.s545 # CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00]
547 # CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88]
551 # CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02]
553 # CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88]
558 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
561 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
565 # CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
567 # CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88]
572 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
575 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
[all …]
Dmicromips-loadstore-unaligned.s12 # CHECK-EL: lwl $4, 16($5) # encoding: [0x85,0x60,0x10,0x00]
19 # CHECK-EB: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
23 lwl $4, 16($5)
Dmips64-expansions.s199 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
209 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
218 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
228 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
238 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
249 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
259 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
270 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
Dsym-offset.ll12 ; check that the immediate fields of lwl and lwr are three apart.
13 ; 8841000e lwl at,14(v0)
Dnacl-mask.s51 lwl $4, 0($9)
90 # CHECK-NEXT: lwl $4, 0($9)
/external/valgrind/none/tests/mips32/
Dunaligned_load_store.stdout.exp-BE1 PRE lwl
9 POST lwl
Dunaligned_load_store.stdout.exp-LE1 PRE lwl
9 POST lwl
DMIPS32int.stdout.exp-mips32-LE259 lwl $t0, 0($t1) :: rt 0x1f000000
260 lwl $t0, 4($t1) :: rt 0x00000000
261 lwl $t0, 8($t1) :: rt 0x03000000
262 lwl $t0, 12($t1) :: rt 0xff000000
263 lwl $t0, 16($t1) :: rt 0x2f000000
264 lwl $t0, 20($t1) :: rt 0x2b000000
265 lwl $t0, 24($t1) :: rt 0x2b000000
266 lwl $t0, 28($t1) :: rt 0x2a000000
267 lwl $t0, 32($t1) :: rt 0x3e000000
268 lwl $t0, 36($t1) :: rt 0x3c000000
[all …]
DMIPS32int.stdout.exp-mips32-BE259 lwl $t0, 0($t1) :: rt 0x121f1e1f
260 lwl $t0, 4($t1) :: rt 0x00000000
261 lwl $t0, 8($t1) :: rt 0x00000003
262 lwl $t0, 12($t1) :: rt 0xffffffff
263 lwl $t0, 16($t1) :: rt 0x232f2e2f
264 lwl $t0, 20($t1) :: rt 0x242c2b2b
265 lwl $t0, 24($t1) :: rt 0x252a2e2b
266 lwl $t0, 28($t1) :: rt 0x262d2d2a
267 lwl $t0, 32($t1) :: rt 0x3f343f3e
268 lwl $t0, 36($t1) :: rt 0x3e353d3c
[all …]
DMIPS32int.stdout.exp-mips32r2-LE645 lwl $t0, 0($t1) :: rt 0x1f000000
646 lwl $t0, 4($t1) :: rt 0x00000000
647 lwl $t0, 8($t1) :: rt 0x03000000
648 lwl $t0, 12($t1) :: rt 0xff000000
649 lwl $t0, 16($t1) :: rt 0x2f000000
650 lwl $t0, 20($t1) :: rt 0x2b000000
651 lwl $t0, 24($t1) :: rt 0x2b000000
652 lwl $t0, 28($t1) :: rt 0x2a000000
653 lwl $t0, 32($t1) :: rt 0x3e000000
654 lwl $t0, 36($t1) :: rt 0x3c000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE645 lwl $t0, 0($t1) :: rt 0x121f1e1f
646 lwl $t0, 4($t1) :: rt 0x00000000
647 lwl $t0, 8($t1) :: rt 0x00000003
648 lwl $t0, 12($t1) :: rt 0xffffffff
649 lwl $t0, 16($t1) :: rt 0x232f2e2f
650 lwl $t0, 20($t1) :: rt 0x242c2b2b
651 lwl $t0, 24($t1) :: rt 0x252a2e2b
652 lwl $t0, 28($t1) :: rt 0x262d2d2a
653 lwl $t0, 32($t1) :: rt 0x3f343f3e
654 lwl $t0, 36($t1) :: rt 0x3e353d3c
[all …]
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
Dinvalid-mips3-wrong-error.s16 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm/test/MC/Mips/mips1/
Dvalid.s60 lwl $s4,-4231($15)
167 lwl $3, %lo(g_8)($2) # CHECK: encoding: [0x88,0x43,A,A]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s80 lwl $s4,-4231($15)
194 lwl $3, %lo(g_8)($2) # CHECK: encoding: [0x88,0x43,A,A]
/external/llvm/test/MC/Mips/mips32/
Dvalid.s87 lwl $s4,-4231($15)
224 lwl $3, %lo(g_8)($2) # CHECK: encoding: [0x88,0x43,A,A]

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