Searched refs:mcInst (Results 1 – 2 of 2) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 152 static void translateRegister(MCInst &mcInst, Reg reg) { in translateRegister() argument
161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
170 static void translateImmediate(MCInst &mcInst, uint64_t immediate, in translateImmediate() argument
198 uint32_t Opcode = mcInst.getOpcode(); in translateImmediate()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
256 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
265 static bool translateRMRegister(MCInst &mcInst, in translateRMRegister() argument
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
303 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) { in translateRMMemory() argument
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 248 static void translateRegister(MCInst &mcInst, Reg reg) { in translateRegister() argument
257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { in translateSrcIndex() argument
326 mcInst.addOperand(baseReg); in translateSrcIndex()
330 mcInst.addOperand(segmentReg); in translateSrcIndex()
339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { in translateDstIndex() argument
351 mcInst.addOperand(baseReg); in translateDstIndex()
361 static void translateImmediate(MCInst &mcInst, uint64_t immediate, in translateImmediate() argument
419 switch (mcInst.getOpcode()) { in translateImmediate()
447 mcInst.setOpcode(NewOpc); in translateImmediate()
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