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/external/valgrind/none/tests/mips32/
DMoveIns.stdout.exp-BE114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
122 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
123 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
DMoveIns.stdout.exp114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
122 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
123 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
/external/valgrind/none/tests/mips64/
Dmove_instructions.stdout.exp-BE1026 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1027 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1028 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1029 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1030 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1031 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1032 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1033 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1034 movf.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 0
1035 movf.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 0
[all …]
Dmove_instructions.stdout.exp-LE1026 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1027 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1028 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1029 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1030 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1031 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1032 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1033 movf.s $f4, $f6, $fcc0 :: out: 0x0, cc: 1
1034 movf.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 0
1035 movf.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 0
[all …]
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s12 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
13 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
15 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
17 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s13 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
14 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
16 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
18 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
26 movf $9, $6, $fcc0
Dmips-fpu-instructions.s163 # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
166 # CHECK: movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46]
167 # CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
198 movf $2, $1, $fcc0
201 movf.d $f4, $f6, $fcc2
202 movf.s $f4, $f6, $fcc5
Dmicromips-fpu-instructions.s64 # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
65 # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
129 # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
130 # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
190 movf.s $f4, $f6, $fcc0
191 movf.d $f4, $f6, $fcc0
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll44 ; 32-C: movf $2, $zero, $fcc0
48 ; 64-C: movf $2, $zero, $fcc0
61 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
146 ; 32-C: movf $2, $zero, $fcc0
150 ; 64-C: movf $2, $zero, $fcc0
163 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
180 ; 32-C: movf $2, $zero, $fcc0
184 ; 64-C: movf $2, $zero, $fcc0
197 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
288 ; 32-C: movf $2, $zero, $fcc0
[all …]
Dselect.ll281 ; 32: movf.s $f14, $f12, $fcc0
287 ; 32R2: movf.s $f14, $f12, $fcc0
296 ; 64: movf.s $f13, $f12, $fcc0
300 ; 64R2: movf.s $f13, $f12, $fcc0
318 ; 32: movf.d $f14, $f12, $fcc0
324 ; 32R2: movf.d $f14, $f12, $fcc0
333 ; 64: movf.d $f13, $f12, $fcc0
337 ; 64R2: movf.d $f13, $f12, $fcc0
429 ; 32: movf.d $f14, $f12, $fcc0
435 ; 32R2: movf.d $f14, $f12, $fcc0
[all …]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s22 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
23 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
25 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
26 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
27 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips32r2.s31 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
32 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
34 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
35 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
36 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s50 …movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
51 … movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
52 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
53 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
55 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips4.s52 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
53 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 …movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
55 … movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
57 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dselect.ll51 ; CHECK: movf.s
60 ; CHECK: movf.d
87 ; CHECK: movf.d
96 ; CHECK: movf.s
123 ; CHECK: movf
154 ; CHECK: movf
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll198 ; CMOV-32: movf.s $f14, $f12, $fcc0
205 ; CMOV-64: movf.s $f13, $f12, $fcc0
212 ; MM32R3: movf.s $f14, $f12, $fcc0
235 ; CMOV-32: movf.s $f14, $f12, $fcc0
242 ; CMOV-64: movf.s $f13, $f12, $fcc0
249 ; MM32R3: movf.s $f14, $f12, $fcc0
309 ; CMOV-32: movf.s $f14, $f12, $fcc0
319 ; CMOV-64: movf.s $f13, $f12, $fcc0
329 ; MM32R3: movf.s $f14, $f12, $fcc0
Dselect-dbl.ll221 ; CMOV-32: movf.d $f14, $f12, $fcc0
228 ; CMOV-64: movf.d $f13, $f12, $fcc0
235 ; MM32R3: movf.d $f14, $f12, $fcc0
258 ; CMOV-32: movf.d $f14, $f12, $fcc0
265 ; CMOV-64: movf.d $f13, $f12, $fcc0
272 ; MM32R3: movf.d $f14, $f12, $fcc0
332 ; CMOV-32: movf.d $f14, $f12, $fcc0
342 ; CMOV-64: movf.d $f13, $f12, $fcc0
352 ; MM32R3: movf.d $f14, $f12, $fcc0
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s14 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll47 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
88 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
128 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
168 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
208 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
248 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips4.s55 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
56 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
57 …movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
58 … movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
59 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
60 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips5.s54 …movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
55 … movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 …movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
57 … movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
58 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
59 … movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips64.s26 …movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
27 …movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
28 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/lib/Target/Mips/
DMipsCondMov.td172 def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
176 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
181 def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
187 def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
194 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
/external/llvm/test/MC/Mips/mips32/
Dvalid.s102 movf $gp,$8,$fcc7
103 movf.d $f6,$f11,$fcc5
104 movf.s $f23,$f5,$fcc6

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