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/external/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-aliases.s166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #16
[all …]
Darm64-tls-relocs.s44 movn x4, #:tprel_g2:var
55 movn x6, #:tprel_g1:var
81 movn x12, #:tprel_g0:var
168 movn x4, #:dtprel_g2:var
179 movn x6, #:dtprel_g1:var
205 movn x12, #:dtprel_g0:var
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
/external/valgrind/none/tests/mips32/
DMoveIns.stdout.exp-BE193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
202 movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-int.ll46 ; CMOV: movn $6, $5, $[[T0]]
55 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
81 ; CMOV: movn $6, $5, $[[T0]]
90 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
116 ; CMOV: movn $6, $5, $[[T0]]
125 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
158 ; CMOV-32: movn $2, $6, $[[T0]]
160 ; CMOV-32: movn $3, $7, $[[T0]]
181 ; CMOV-64: movn $6, $5, $[[T0]]
193 ; MM32R3: movn $2, $6, $[[T0]]
[all …]
Dlshr.ll106 ; 32R1-R5: movn $3, $[[T4]], $[[T5]]
108 ; 32R1-R5: movn $2, $zero, $[[T5]]
132 ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
134 ; MMR3: movn $2, $[[T8]], $[[T6]]
184 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
186 ; GP64-NOT-R6: movn $2, $zero, $1
Dashr.ll108 ; 32R1-R5: movn $3, $[[T4]], $[[T5]]
111 ; 32R1-R5: movn $2, $4, $[[T5]]
138 ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
140 ; MMR3: movn $2, $[[T8]], $[[T6]]
193 ; GP64-NOT-R6: movn $3, $2, $[[T5]]
196 ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
Dshl.ll122 ; 32R1-R5: movn $2, $[[T4]], $[[T5]]
124 ; 32R1-R5: movn $3, $zero, $[[T5]]
148 ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
150 ; MMR3: movn $3, $[[T8]], $[[T6]]
200 ; GP64-NOT-R6: movn $2, $3, $[[T5]]
202 ; GP64-NOT-R6: movn $3, $zero, $1
Dselect-flt.ll50 ; CMOV-32: movn.s $f0, $f1, $[[T0]]
58 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
67 ; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
88 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
95 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
102 ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll12 ; CHECK-NEXT: movn $6, $5, $[[T2]]
29 ; CHECK-NEXT: movn $6, $5, $[[T4]]
46 ; CHECK-NEXT: movn $6, $5, $[[T4]]
61 ; CHECK-NEXT: movn $6, $5, $[[T2]]
77 ; CHECK: movn.s $f0, $f1, $[[T2]]
93 ; CHECK: movn.d $f0, $f2, $[[T2]]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
Dmicromips-fpu-instructions.s60 # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
61 # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
125 # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
126 # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
186 movn.s $f4, $f6, $7
187 movn.d $f4, $f6, $7
/external/llvm/test/CodeGen/Mips/
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
128 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
138 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
201 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
216 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
Dselect.ll15 ; 32: movn $5, $6, $4
18 ; 32R2: movn $5, $6, $4
25 ; 64: movn $5, $6, $4
28 ; 64R2: movn $5, $6, $4
45 ; 32-DAG: movn $6, $[[F1]], $4
47 ; 32: movn $7, $[[F1H]], $4
52 ; 32R2-DAG: movn $6, $[[F1]], $4
54 ; 32R2: movn $7, $[[F1H]], $4
67 ; 64: movn $5, $6, $4
70 ; 64R2: movn $5, $6, $4
[all …]
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class3_chroma.s137 movn x20,#0
146 movn x20,#0
173 movn x20,#0
182 movn x20,#0
222 movn x20,#0
231 movn x20,#0
260 movn x20,#0
269 movn x20,#0
423 movn x20,#0
431 movn x20,#0
[all …]
Dihevc_sao_edge_offset_class2_chroma.s142 movn x20,#0
150 movn x20,#0
181 movn x20,#0
188 movn x20,#0
230 movn x20,#0
240 movn x20,#0
269 movn x20,#0
279 movn x20,#0
439 movn x20,#0
446 movn x20,#0
[all …]
Dihevc_sao_edge_offset_class2.s125 movn x20,#0
134 movn x20,#0
172 movn x20,#0
178 movn x20,#0
312 movn x20,#0
386 movn x20,#0
400 movn x20,#0
490 movn x20,#0
631 movn x20,#0
764 movn x20,#0
Dihevc_sao_edge_offset_class3.s130 movn x20,#0
137 movn x20,#0
179 movn x20,#0
185 movn x20,#0
325 movn x20,#0
389 movn x20,#0
419 movn x20,#0
520 movn x20,#0
669 movn x20,#0
813 movn x20,#0
/external/llvm/lib/Target/Mips/
DMipsCondMov.td119 def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
123 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
125 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
127 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
138 def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
142 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
148 def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
155 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
160 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32.s17 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
18 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
19 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s18 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
19 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
20 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s19 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
20 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
21 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s28 …movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
29 …movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
30 …movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…

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