Home
last modified time | relevance | path

Searched refs:movt (Results 1 – 25 of 186) sorted by relevance

12345678

/external/llvm/test/MC/ARM/
Dtarget-expressions.s19 movt r0, :upper16:function
22 movt r1, #:upper16:function
25 movt r2, :upper16:deadbeat
28 movt r3, #:upper16:deadbeat
31 movt r4, :upper16:0xD1510D6E
34 movt r5, #:upper16:0xD1510D6E
37 movt r0, :upper16:external
40 movt r1, #:upper16:external
43 movt r2, #:upper16:(16 + 16)
46 movt r3, :upper16:(16 + 16)
[all …]
Dmacho-movwt.s6 movt r0, :upper16:_x
9 movt r0, :upper16:_x+4
12 movt r0, :upper16:_x+0x10000
16 movt r0, :upper16:_x
19 movt r0, :upper16:_x+4
22 movt r0, :upper16:_x+0x10000
Dthumb2be-movt-encoding.s4 movt r9, :upper16:(_bar) label
5 @ CHECK-LE: movt r9, :upper16:_bar @ encoding: [0xc0'A',0xf2'A',0b0000AAAA,0x09]
7 @ CHECK-BE: movt r9, :upper16:_bar @ encoding: [0xf2,0b1100AAAA,0x09'A',A]
/external/valgrind/none/tests/mips32/
DMoveIns.stdout.exp-BE227 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
228 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
229 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
231 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
232 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
234 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
236 movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dmovt-movw-global.ll11 ; EABI-NEXT: movt r0, :upper16:foo
14 ; IOS-NEXT: movt r0, :upper16:L_foo$non_lazy_ptr
17 ; IOS-PIC-NEXT: movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+8))
20 ; IOS-STATIC-NOT: movt r0, :upper16:_foo
27 ; EABI-NEXT: movt r1, :upper16:foo
30 ; IOS-NEXT: movt r1, :upper16:L_foo$non_lazy_ptr
33 ; IOS-PIC-NEXT: movt r1, :upper16:(L_foo$non_lazy_ptr-(LPC1_0+8))
36 ; IOS-STATIC-NOT: movt r1, :upper16:_foo
/external/llvm/test/CodeGen/ARM/
Dmovt-movw-global.ll11 ; EABI-NEXT: movt r0, :upper16:foo
14 ; IOS-NEXT: movt r0, :upper16:L_foo$non_lazy_ptr
17 ; IOS-PIC-NEXT: movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+8))
20 ; IOS-STATIC-NEXT: movt r0, :upper16:_foo
27 ; EABI-NEXT: movt r1, :upper16:foo
30 ; IOS-NEXT: movt r1, :upper16:L_foo$non_lazy_ptr
33 ; IOS-PIC-NEXT: movt r1, :upper16:(L_foo$non_lazy_ptr-(LPC1_0+8))
36 ; IOS-STATIC-NEXT: movt r1, :upper16:_foo
Dsubtarget-no-movt.ll2 ; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=-no-movt | FileChec…
3 ; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+no-movt | FileChec…
5 ; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-no-movt | File…
6 ; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+no-movt | File…
15 ; USE-MOVT: movt [[R0]], #35037
29 ; NO-OPTION: movt [[R0]], #35037
33 ; USE-MOVT: movt [[R0]], #35037
45 attributes #0 = { "target-features"="+no-movt" }
Dfast-isel-intrinsic.ll9 ; movw/movt or constant pool loads. Different platforms will select
18 ; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
27 ; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}}
31 ; ARM-LONG-ELF: movt r3, :upper16:memset
36 ; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
44 ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
57 ; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
61 ; ARM-ELF: movt r0, :upper16:temp
73 ; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}}
77 ; ARM-LONG-ELF: movt r3, :upper16:memcpy
[all …]
Dldm-stm-base-materialization.ll13 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
14 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
32 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
33 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
53 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
54 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
74 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
75 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
Ddarwin-tls.ll2 ; RUN: llc -mtriple=thumbv7s-apple-ios7.0 -o - %s -mattr=+no-movt | FileCheck %s --check-prefix=T2-…
4 ; RUN: llc -mtriple=thumbv7s-apple-ios7.0 -o - %s -mattr=+no-movt -relocation-model=static | FileCh…
6 ; RUN: llc -mtriple=armv7s-apple-ios7.0 -o - %s -mattr=+no-movt | FileCheck %s --check-prefix=ARM-L…
8 ; RUN: llc -mtriple=armv7s-apple-ios7.0 -o - %s -mattr=+no-movt -relocation-model=static | FileChec…
19 ; T2-MOVT-PIC: movt r0, :upper16:(_local_tls_var-([[PCREL_LOC]]+4))
38 ; T2-MOVT-STATIC: movt r0, :upper16:_local_tls_var
53 ; ARM-MOVT-PIC: movt [[VARPC1]], :upper16:(_local_tls_var-([[PCREL_LOC1]]+8))
57 ; ARM-MOVT-PIC: movt [[VARPC2]], :upper16:(_local_tls_var-([[PCREL_LOC2]]+8))
75 ; ARM-MOVT-STATIC: movt r0, :upper16:_local_tls_var
96 ; T2-MOVT-PIC: movt r[[EXTGOT]], :upper16:(L_external_tls_var$non_lazy_ptr-([[PCREL_LOC]]+4))
[all …]
D2011-11-29-128bitArithmetics.ll10 ; CHECK: movt r1, :upper16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}}
188 ; CHECK: movt [[reg0]], :upper16:{{.*}}
220 ; CHECK: movt [[reg0]], :upper16:{{.*}}
254 ; CHECK: movt [[reg0]], :upper16:{{.*}}
277 ; CHECK: movt [[reg0]], :upper16:{{.*}}
[all …]
Dfast-isel-call.ll12 ; movw/movt or constant pool loads. Different platforms will select
116 ; ARM-LONG-MACHO: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
120 ; ARM-LONG-ELF: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
141 ; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
157 ; ARM: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
161 ; THUMB: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
177 ; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
181 ; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv
188 ; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
219 ; ARM-NOVFP: movt r0, #16611
[all …]
/external/valgrind/none/tests/mips64/
Dmove_instructions.stdout.exp-BE1094 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1095 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1096 movt.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 1
1097 movt.s $f4, $f6, $fcc0 :: out: 0x44db0000, cc: 1
1098 movt.s $f4, $f6, $fcc0 :: out: 0x322bcc77, cc: 1
1099 movt.s $f4, $f6, $fcc0 :: out: 0x44ad1333, cc: 1
1100 movt.s $f4, $f6, $fcc0 :: out: 0x4e6e6b28, cc: 1
1101 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1102 movt.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 1
1103 movt.s $f4, $f6, $fcc0 :: out: 0x0, cc: 0
[all …]
Dmove_instructions.stdout.exp-LE1094 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1095 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1096 movt.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 1
1097 movt.s $f4, $f6, $fcc0 :: out: 0x44db0000, cc: 1
1098 movt.s $f4, $f6, $fcc0 :: out: 0x322bcc77, cc: 1
1099 movt.s $f4, $f6, $fcc0 :: out: 0x44ad1333, cc: 1
1100 movt.s $f4, $f6, $fcc0 :: out: 0x4e6e6b28, cc: 1
1101 movt.s $f4, $f6, $fcc0 :: out: 0xc8a9da0f, cc: 1
1102 movt.s $f4, $f6, $fcc0 :: out: 0xbf800000, cc: 1
1103 movt.s $f4, $f6, $fcc0 :: out: 0x0, cc: 0
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-mov.ll40 ;CHECK: movt r1, #427
81 ;CHECK: movt r1, #4267
98 ;CHECK: movt r1, #43947
107 ;CHECK: movt r1, #43947
116 ;CHECK: movt r1, #43962
125 ;CHECK: movt r1, #47787
170 ; CHECK: movt r0, #1234
180 ; CHECK: movt r0, #1234
193 ; CHECK: movt r0, #1234
207 ; CHECK: movt r0, #1234
/external/llvm/test/CodeGen/Thumb/
Dldm-stm-base-materialization-thumb2.ll13 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
14 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
32 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
33 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
53 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
54 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
74 ; CHECK: movt [[LB:[rl0-9]+]], :upper16:b
75 ; CHECK: movt [[SB:[rl0-9]+]], :upper16:a
/external/llvm/test/CodeGen/ARM/Windows/
Dmovw-movt-relocations.ll20 ; CHECK-WINDOWS-NEXT: movt r[[i]], :upper16:i
22 ; CHECK-WINDOWS-NEXT: movt r[[j]], :upper16:j
26 ; CHECK-EABI-NEXT: movt r[[i]], :upper16:i
27 ; CHECK-EABI-NEXT: movt r[[j]], :upper16:j
Ddllimport.ll17 ; CHECK: movt r0, :upper16:__imp_var
29 ; CHECK: movt r0, :upper16:ext
39 ; CHECK: movt r0, :upper16:__imp_var
50 ; CHECK: movt r0, :upper16:__imp_external
Dtls.ll19 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
40 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
61 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
82 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
103 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
124 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
145 ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-mov.ll40 ;CHECK: movt r1, #427
81 ;CHECK: movt r1, #4267
98 ;CHECK: movt r1, #43947
107 ;CHECK: movt r1, #43947
116 ;CHECK: movt r1, #43962
125 ;CHECK: movt r1, #47787
170 ; CHECK: movt r0, #1234
180 ; CHECK: movt r0, #1234
193 ; CHECK: movt r0, #1234
207 ; CHECK: movt r0, #1234
/external/llvm/test/CodeGen/Mips/
Dselect.ll207 ; 32: movt.s $f14, $f12, $fcc0
213 ; 32R2: movt.s $f14, $f12, $fcc0
222 ; 64: movt.s $f13, $f12, $fcc0
226 ; 64R2: movt.s $f13, $f12, $fcc0
244 ; 32: movt.s $f14, $f12, $fcc0
250 ; 32R2: movt.s $f14, $f12, $fcc0
259 ; 64: movt.s $f13, $f12, $fcc0
263 ; 64R2: movt.s $f13, $f12, $fcc0
355 ; 32: movt.d $f14, $f12, $fcc0
361 ; 32R2: movt.d $f14, $f12, $fcc0
[all …]
Dfcmp.ll78 ; 32-C: movt $2, $zero, $fcc0
82 ; 64-C: movt $2, $zero, $fcc0
95 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
112 ; 32-C: movt $2, $zero, $fcc0
116 ; 64-C: movt $2, $zero, $fcc0
129 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
214 ; 32-C: movt $2, $zero, $fcc0
218 ; 64-C: movt $2, $zero, $fcc0
233 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
251 ; 32-C: movt $2, $zero, $fcc0
[all …]
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s21 …movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
22 … movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
23 …movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
24 …movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
25 … movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
25 movt $9, $6, $fcc0
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dselect.ll33 ; CHECK: movt.s
42 ; CHECK: movt.s
69 ; CHECK: movt.d
78 ; CHECK: movt.d
105 ; CHECK: movt
114 ; CHECK: movt
132 ; CHECK: movt
143 ; CHECK: movt

12345678