| /external/llvm/test/CodeGen/ARM/ |
| D | shifter_operand.ll | 71 ; CHECK-THUMB: muls r1, r2, r1
82 ; CHECK-THUMB: muls r1, r2, r1
94 ; CHECK-THUMB: muls r1, r2, r1
106 ; CHECK-THUMB: muls r1, r2, r1
118 ; CHECK-THUMB: muls r1, r2, r1
130 ; CHECK-THUMB: muls r1, r2, r1
142 ; CHECK-THUMB: muls r1, r2, r1
156 ; CHECK-THUMB: muls r1, r2, r1
170 ; CHECK-THUMB: muls r1, r2, r1
184 ; CHECK-THUMB: muls r1, r2, r1
[all …]
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| D | avoid-cpsr-rmw.ll | 10 ; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2
12 ; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0
14 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
31 ; CHECK-NOT: muls
64 ; CHECK: muls
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| D | gep-optimization.ll | 12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
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| D | urem-opt-size.ll | 3 ; expanded to a sequence of umull, lsrs, muls and sub instructions, but
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| D | indirectbr.ll | 50 ; THUMB: muls
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | avoid-cpsr-rmw.ll | 9 ; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
11 ; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
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| D | indirectbr.ll | 44 ; THUMB: muls
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-mla.ll | 13 ; NO_MULOPS: muls r0, r1, r0
24 ; NO_MULOPS: muls r0, r1, r0
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| D | thumb2-mls.ll | 18 ; CHECK: muls r0, r1, r0
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| D | thumb2-mul.ll | 5 ; CHECK: muls r0, r1, r0
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| /external/llvm/test/MC/ARM/ |
| D | mul-v4.s | 6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
10 muls r0, r1, r2 label
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| D | basic-thumb-instructions.s | 423 muls r1, r2, r1
424 muls r2, r2, r3
425 muls r3, r4
427 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
428 @ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
429 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
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| D | thumb-diagnostics.s | 164 muls r1, r2, r3
166 @ CHECK-ERRORS: muls r1, r2, r3
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| D | thumb2-mls.ll | 18 ; CHECK: muls r0, r0, r1
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| D | thumb2-mul.ll | 5 ; CHECK: muls r0, r0, r1
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 374 muls r1, r2, r1
375 muls r3, r4
377 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
378 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
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| D | thumb-diagnostics.s | 92 muls r1, r2, r3
94 @ CHECK-ERRORS: muls r1, r2, r3
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| D | basic-arm-instructions.s | 975 muls r5, r6, r7
980 @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
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| D | basic-thumb2-instructions.s | 1210 muls r3, r4, r3
1216 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 279 # CHECK: muls r1, r2, r1
280 # CHECK: muls r3, r4
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 296 # CHECK: muls r1, r2, r1
297 # CHECK: muls r3, r4
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rdlow-rnlow-rmlow-t32.cc | 51 #define FOREACH_INSTRUCTION(M) M(muls)
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| D | test-assembler-cond-rd-rn-rm-a32.cc | 53 M(muls) \
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| /external/valgrind/none/tests/arm/ |
| D | v6intARM.stdout.exp | 502 muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
503 muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
504 muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000 Z
505 muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
506 muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
507 muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N
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| D | v6intThumb.stdout.exp | 228 muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 0, cpsr 0x80000000 N
229 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
230 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
231 muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
232 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
233 muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
234 muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
235 muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 1, cpsr 0x90000000 N V
236 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
237 muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
[all …]
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