| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | 2008-08-01-AsmInline.ll | 4 ; RUN: grep multu %t | count 1
12 …%asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwi…
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-alu-instructions.s | 38 # CHECK-EL: multu $9, $7 # encoding: [0xe9,0x00,0x3c,0x9b]
81 # CHECK-EB: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c]
122 multu $9, $7
|
| D | mips64-alu-instructions.s | 83 # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
108 multu $3,$5
|
| D | mips-alu-instructions.s | 87 # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
112 multu $3,$5
|
| /external/llvm/test/CodeGen/Mips/ |
| D | 2008-08-01-AsmInline.ll | 8 ; CHECK: multu
11 …%asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwi…
|
| D | mulll.ll | 13 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
|
| D | mulull.ll | 14 ; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 23 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
24 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips2.s | 29 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
30 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/dsp/ |
| D | valid.s | 78 …multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x…
80 …multu $4, $5 # CHECK: multu $4, $5 # encoding: [0x00,0x…
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips1.s | 26 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
27 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips3.s | 22 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
23 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips2.s | 32 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
33 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips64.s | 43 …multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
44 …multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 492 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
493 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
494 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
495 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
496 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
497 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
498 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
499 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
500 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
501 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32-BE | 492 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
493 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
494 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
495 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
496 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
497 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
498 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
499 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
500 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
501 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-LE | 878 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
879 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
880 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
881 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
882 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
883 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
884 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
885 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
886 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
887 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-BE | 878 multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
879 multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
880 multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
881 multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
882 multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
883 multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
884 multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
885 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
886 multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
887 multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
[all …]
|
| /external/llvm/test/MC/Mips/dspr2/ |
| D | valid.s | 106 …multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x85,0…
108 …multu $4, $5 # CHECK: multu $4, $5 # encoding: [0x00,0x85,0…
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 179 ; M2: multu $5, $7
185 ; 32R1-R5: multu $5, $7
208 ; MM32R3: multu $[[T0:[0-9]+]], $7
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 78 multu $gp,$k0
79 multu $9,$s2
|
| /external/llvm/test/MC/Mips/micromips-dsp/ |
| D | valid.s | 35 multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| D | valid-mips1-el.txt | 73 0x19 0x00 0x9a 0x03 # CHECK: multu $gp, $26
74 0x19 0x00 0x32 0x01 # CHECK: multu $9, $18
|
| D | valid-mips1.txt | 28 0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
39 0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 98 multu $gp,$k0
99 multu $9,$s2
|