| /external/opencv/cvaux/src/ |
| D | cvvideo.cpp | 53 CvMat odd_stub, *odd = (CvMat*)fieldOdd; in cvDeInterlace() local
59 CV_CALL( odd = cvGetMat( odd, &odd_stub )); in cvDeInterlace()
61 if( !CV_ARE_TYPES_EQ( frame, even ) || !CV_ARE_TYPES_EQ( frame, odd )) in cvDeInterlace()
64 if( frame->cols != even->cols || frame->cols != odd->cols || in cvDeInterlace()
65 frame->rows != even->rows*2 || odd->rows != even->rows ) in cvDeInterlace()
75 memcpy( odd->data.ptr + even->step*y, in cvDeInterlace()
|
| /external/llvm/test/MC/Mips/ |
| D | update-module-level-options.s | 6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
|
| D | set-oddspreg-nooddspreg-error.s | 6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
|
| D | nooddspreg-error.s | 9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
|
| /external/eigen/Eigen/src/Geometry/ |
| D | EulerAngles.h | 48 const Index odd = ((a0+1)%3 == a1) ? 0 : 1; in eulerAngles() local
50 const Index j = (a0 + 1 + odd)%3; in eulerAngles()
51 const Index k = (a0 + 2 - odd)%3; in eulerAngles()
56 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) in eulerAngles()
91 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) { in eulerAngles()
106 if (!odd) in eulerAngles()
|
| /external/clang/test/Analysis/ |
| D | NewDelete-path-notes.cpp | 23 void test(Odd *odd) { in test() argument
24 odd->kill(); // expected-note{{Calling 'Odd::kill'}} in test()
26 delete odd; // expected-warning {{Attempt to free released memory}} in test()
|
| /external/pdfium/third_party/zlib_v128/ |
| D | crc32.c | 363 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ in crc32_combine_() local
370 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */ in crc32_combine_()
373 odd[n] = row; in crc32_combine_()
378 gf2_matrix_square(even, odd); in crc32_combine_()
381 gf2_matrix_square(odd, even); in crc32_combine_()
387 gf2_matrix_square(even, odd); in crc32_combine_()
397 gf2_matrix_square(odd, even); in crc32_combine_()
399 crc1 = gf2_matrix_times(odd, crc1); in crc32_combine_()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNopFiller.cpp | 60 odd = 3 } SPUOpPlace; enumerator
93 if( isEvenPlace && this_optype == odd && next_optype == even ) { in runOnMachineBasicBlock()
102 else if ( !isEvenPlace && this_optype == even && next_optype == odd){ in runOnMachineBasicBlock()
119 if (getOpPlacement( *J ) == odd) { in runOnMachineBasicBlock()
146 case 1: retval = odd; break; in getOpPlacement()
|
| /external/syslinux/com32/lib/zlib/ |
| D | crc32.c | 380 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
387 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
390 odd[n] = row;
395 gf2_matrix_square(even, odd);
398 gf2_matrix_square(odd, even);
404 gf2_matrix_square(even, odd);
414 gf2_matrix_square(odd, even);
416 crc1 = gf2_matrix_times(odd, crc1);
|
| /external/zlib/src/ |
| D | crc32.c | 363 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
370 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
373 odd[n] = row;
378 gf2_matrix_square(even, odd);
381 gf2_matrix_square(odd, even);
387 gf2_matrix_square(even, odd);
397 gf2_matrix_square(odd, even);
399 crc1 = gf2_matrix_times(odd, crc1);
|
| /external/llvm/test/CodeGen/Mips/ |
| D | no-odd-spreg-msa.ll | 12 ; Force the float into an odd-numbered register using named registers and
19 ; The intention is that if odd single precision registers are permitted, the
23 ; On the other hand, if odd single precision registers are not permitted, it
46 ; Force the float into an odd-numbered register using named registers and
53 ; The intention is that if odd single precision registers are permitted, the
57 ; On the other hand, if odd single precision registers are not permitted, it
85 ; The intention is that if odd single precision registers are permitted, the
88 ; On the other hand, if odd single precision registers are not permitted, it
113 ; The intention is that if odd single precision registers are permitted, the
116 ; On the other hand, if odd single precision registers are not permitted, it
|
| /external/llvm/test/Transforms/LoopVectorize/PowerPC/ |
| D | stride-vectorization.ll | 19 %odd.idx = add nsw i64 %0, 1
22 %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
25 %2 = load double, double* %arrayidx.odd, align 8
|
| /external/selinux/secilc/docs/ |
| D | cil_xen_statements.md | 25 <tr class="odd">
35 <tr class="odd">
65 <tr class="odd">
75 <tr class="odd">
105 <tr class="odd">
113 <tr class="odd">
143 <tr class="odd">
151 <tr class="odd">
181 <tr class="odd">
189 <tr class="odd">
|
| D | cil_user_statements.md | 21 <tr class="odd">
57 <tr class="odd">
65 <tr class="odd">
99 <tr class="odd">
135 <tr class="odd">
143 <tr class="odd">
193 <tr class="odd">
201 <tr class="odd">
239 <tr class="odd">
247 <tr class="odd">
[all …]
|
| D | cil_role_statements.md | 21 <tr class="odd">
59 <tr class="odd">
67 <tr class="odd">
101 <tr class="odd">
137 <tr class="odd">
145 <tr class="odd">
201 <tr class="odd">
209 <tr class="odd">
237 <tr class="odd">
245 <tr class="odd">
[all …]
|
| D | cil_conditional_statements.md | 21 <tr class="odd">
29 <tr class="odd">
66 <tr class="odd">
74 <tr class="odd">
88 <tr class="odd">
135 <tr class="odd">
143 <tr class="odd">
178 <tr class="odd">
186 <tr class="odd">
200 <tr class="odd">
|
| D | cil_container_statements.md | 24 <tr class="odd">
32 <tr class="odd">
64 <tr class="odd">
72 <tr class="odd">
80 <tr class="odd">
112 <tr class="odd">
120 <tr class="odd">
128 <tr class="odd">
219 <tr class="odd">
227 <tr class="odd">
[all …]
|
| D | cil_class_and_permission_statements.md | 21 <tr class="odd">
29 <tr class="odd">
59 <tr class="odd">
67 <tr class="odd">
99 <tr class="odd">
107 <tr class="odd">
159 <tr class="odd">
216 <tr class="odd">
248 <tr class="odd">
256 <tr class="odd">
[all …]
|
| D | cil_type_statements.md | 21 <tr class="odd">
57 <tr class="odd">
89 <tr class="odd">
97 <tr class="odd">
132 <tr class="odd">
166 <tr class="odd">
174 <tr class="odd">
235 <tr class="odd">
243 <tr class="odd">
290 <tr class="odd">
[all …]
|
| D | cil_mls_labeling_statements.md | 23 <tr class="odd">
59 <tr class="odd">
91 <tr class="odd">
99 <tr class="odd">
133 <tr class="odd">
176 <tr class="odd">
212 <tr class="odd">
240 <tr class="odd">
248 <tr class="odd">
280 <tr class="odd">
[all …]
|
| D | cil_file_labeling_statements.md | 21 <tr class="odd">
29 <tr class="odd">
38 <tr class="odd">
46 <tr class="odd">
54 <tr class="odd">
62 <tr class="odd">
70 <tr class="odd">
121 <tr class="odd">
134 <tr class="odd">
187 <tr class="odd">
[all …]
|
| D | cil_default_object_statements.md | 23 <tr class="odd">
31 <tr class="odd">
75 <tr class="odd">
83 <tr class="odd">
122 <tr class="odd">
130 <tr class="odd">
160 <tr class="odd">
168 <tr class="odd">
|
| /external/libvpx/libvpx/vpx_dsp/ppc/ |
| D | bitdepth_conversion_vsx.h | 37 const int32x4_t odd = vec_mulo(v, one); in store_tran_low() local
38 const int32x4_t high = vec_mergeh(even, odd); in store_tran_low()
39 const int32x4_t low = vec_mergel(even, odd); in store_tran_low()
|
| /external/syslinux/core/lwip/src/core/ipv4/ |
| D | inet_chksum.c | 140 int odd = ((mem_ptr_t)pb & 1); in lwip_standard_chksum() local
143 if (odd && len > 0) { in lwip_standard_chksum()
169 if (odd) { in lwip_standard_chksum()
198 int odd = ((mem_ptr_t)pb & 1); in lwip_standard_chksum() local
200 if (odd && len > 0) { in lwip_standard_chksum()
251 if (odd) { in lwip_standard_chksum()
|
| /external/icu/icu4c/source/test/intltest/ |
| D | testidna.cpp | 999 UChar odd[MAX_DEST_SIZE]; in testChaining() local
1012 memcpy(odd,expected,(expectedLen+1) * U_SIZEOF_UCHAR); in testChaining()
1016 evenLen = func(odd,-1,even,MAX_DEST_SIZE,options, &parseError, &status); in testChaining()
1022 oddLen = func(even,-1,odd,MAX_DEST_SIZE,options, &parseError, &status); in testChaining()
1031 u_strCaseCompare(odd,oddLen, expected,expectedLen, 0, &status) !=0 ){ in testChaining()
1037 u_strncmp(odd,expected,expectedLen) !=0 ){ in testChaining()
1049 memcpy(odd,expected,(expectedLen+1) * U_SIZEOF_UCHAR); in testChaining()
1053 … evenLen = func(odd,-1,even,MAX_DEST_SIZE,options|UIDNA_ALLOW_UNASSIGNED, &parseError, &status); in testChaining()
1059 … oddLen = func(even,-1,odd,MAX_DEST_SIZE,options|UIDNA_ALLOW_UNASSIGNED, &parseError, &status); in testChaining()
1068 u_strCaseCompare(odd,oddLen, expected,expectedLen, 0, &status) !=0 ){ in testChaining()
[all …]
|