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Searched refs:opstr (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMicroMipsDSPInstrFormats.td10 class MMDSPInst<string opstr = "">
14 string BaseOpcode = opstr;
25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
61 class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
74 class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
86 class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
99 class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
112 class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
[all …]
DMicroMipsInstrInfo.td185 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
188 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
196 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
199 !strconcat(opstr, "\t$rt, $addr"),
206 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
209 !strconcat(opstr, "\t$rt, $addr"),
229 class MovePMM16<string opstr, RegisterOperand RO> :
231 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
251 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
254 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
[all …]
DMipsInstrFPU.td104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
107 !strconcat(opstr, "\t$fd, $fs, $ft"),
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
113 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
128 multiclass ABSS_M<string opstr, InstrItinClass Itin,
[all …]
DMipsInstrInfo.td1096 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1100 !strconcat(opstr, "\t$rd, $rs, $rt"),
1101 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1108 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1113 !strconcat(opstr, "\t$rt, $rs, $imm16"),
1115 Itin, FrmI, opstr> {
1121 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
1123 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
1130 class LogicNOR<string opstr, RegisterOperand RO>:
1132 !strconcat(opstr, "\t$rd, $rs, $rt"),
[all …]
DMicroMips32r6InstrInfo.td454 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
455 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
457 MMR6Arch<opstr>, MicroMipsR6Inst16 {
464 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
466 : MMR6Arch<opstr> {
468 string AsmString = !strconcat(opstr, "\t$rt, $offset");
486 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
487 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
489 MMR6Arch<opstr>, MicroMipsR6Inst16 {
611 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
[all …]
DMipsCondMov.td19 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
27 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
36 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
39 !strconcat(opstr, "\t$rd, $rs, $fcc"),
41 Itin, FrmFR, opstr>, HARDFLOAT {
46 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
49 !strconcat(opstr, "\t$fd, $fs, $fcc"),
51 Itin, FrmFR, opstr>, HARDFLOAT {
DMicroMips64r6InstrFormats.td105 class POOL32S_ARITH_FM_MMR6<string opstr, bits<9> funct>
106 : MMR6Arch<opstr> {
121 class DADDIU_FM_MMR6<string opstr> : MMR6Arch<opstr> {
DMips64InstrInfo.td354 class Count1s<string opstr, RegisterOperand RO>:
355 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
356 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
360 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
362 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
364 NoItinerary, FrmR, opstr> {
368 class SetCC64_R<string opstr, PatFrag cond_op> :
370 !strconcat(opstr, "\t$rd, $rs, $rt"),
373 II_SEQ_SNE, FrmR, opstr> {
377 class SetCC64_I<string opstr, PatFrag cond_op>:
[all …]
DMicroMips32r6InstrFormats.td14 class MMR6Arch<string opstr> {
16 string BaseOpcode = opstr;
998 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
999 : MipsR6Inst, MMR6Arch<opstr> {
1040 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
DMipsDSPInstrFormats.td47 class DSPInst<string opstr = "">
50 string BaseOpcode = opstr;
DMips32r6InstrFormats.td28 class MipsR6Arch<string opstr> {
30 string BaseOpcode = opstr;
DMicroMips64r6InstrInfo.td193 class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
198 string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
DMipsInstrFormats.td114 InstrItinClass itin, Format f, string opstr = ""> :
117 string BaseOpcode = opstr;
DMips32r6InstrInfo.td437 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
440 : MipsR6Arch<opstr> {
442 string AsmString = !strconcat(opstr, "\t$rt, $offset");
DMicroMipsDSPInstrInfo.td180 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 string AsmString = !strconcat(opstr, "\t$rt, $rs");
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrLoadStore.td138 multiclass PTX_LD<string opstr, string typestr,
142 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
147 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
152 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
157 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
162 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
167 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
172 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC,
176 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
181 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrFPU.td77 class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
80 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))],
84 class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
87 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
91 multiclass FFR1_W_M<bits<6> funct, string opstr> {
92 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
93 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
95 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
101 multiclass FFR1_L_M<bits<6> funct, string opstr> {
102 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
[all …]
DMipsInstrFormats.td272 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
275 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
280 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
283 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
288 class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
291 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
/external/icu/icu4c/source/test/cintltst/
Dputiltst.c316 const char *opstr; in TestCompareVersions() local
324 opstr = testCases[j+1]; in TestCompareVersions()
326 switch(opstr[0]) { in TestCompareVersions()
341 log_verbose("%d: %s %s %s, OK\n", (j/3), v1str, opstr, v2str); in TestCompareVersions()
343 …log_err("%d: %s %s %s: wanted values of the same sign, %d got %d\n", (j/3), v1str, opstr, v2str, o… in TestCompareVersions()
/external/regex-re2/re2/
Dparse.cc2065 StringPiece opstr = t; in Parse()
2083 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2084 if (!ps.PushRepeatOp(op, opstr, nongreedy)) in Parse()
2086 isunary = opstr; in Parse()
2092 StringPiece opstr = t; in Parse() local
2114 opstr.set(opstr.data(), t.data() - opstr.data()); in Parse()
2115 if (!ps.PushRepetition(lo, hi, opstr, nongreedy)) in Parse()
2117 isunary = opstr; in Parse()
/external/google-breakpad/src/third_party/libdisasm/
Dx86_format.c1090 struct op_string * opstr = (struct op_string *) arg; in format_op_raw() local
1092 format_operand_raw(op, insn, opstr->buf, opstr->len); in format_op_raw()
1114 struct op_string opstr = { buf, len }; in format_raw_insn() local
1158 opstr.len = len; in format_raw_insn()
1159 x86_operand_foreach( insn, format_op_raw, &opstr, op_any ); in format_raw_insn()
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td1082 class LoadParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1085 !strconcat(!strconcat("ld.param", opstr),
1088 class LoadParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1091 !strconcat(!strconcat("ld.param", opstr),
1095 class StoreParamScalar4Inst<NVPTXRegClass regclass, string opstr> :
1099 !strconcat(!strconcat("st.param", opstr),
1102 class StoreParamScalar2Inst<NVPTXRegClass regclass, string opstr> :
1105 !strconcat(!strconcat("st.param", opstr),
1108 class StoreRetvalScalar4Inst<NVPTXRegClass regclass, string opstr> :
1112 !strconcat(!strconcat("st.param", opstr),
[all …]
DNVPTXInstrInfo.td1792 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1794 !strconcat(!strconcat("ld.param", opstr),
1798 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1800 !strconcat("ld.param.v2", opstr,
1803 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1807 !strconcat("ld.param.v4", opstr,
1812 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1814 !strconcat("mov", opstr, "\t$dst, retval$b;"),
1818 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1820 !strconcat("st.param", opstr, "\t[param$a+$b], $val;"),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp697 const char* opstr = 0; in LowerOperation() local
699 case ISD::UREM: opstr = "__remqu"; break; in LowerOperation()
700 case ISD::SREM: opstr = "__remq"; break; in LowerOperation()
701 case ISD::UDIV: opstr = "__divqu"; break; in LowerOperation()
702 case ISD::SDIV: opstr = "__divq"; break; in LowerOperation()
706 Addr = DAG.getExternalSymbol(opstr, MVT::i64); in LowerOperation()
/external/selinux/libsepol/cil/src/
Dcil_binary.c2032 const char *opstr = ""; in __cil_expr_to_string() local
2037 opstr = CIL_KEY_OR; in __cil_expr_to_string()
2039 opstr = CIL_KEY_AND; in __cil_expr_to_string()
2041 opstr = CIL_KEY_XOR; in __cil_expr_to_string()
2044 cil_asprintf(out, "%s %s %s", opstr, s1, s2); in __cil_expr_to_string()

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