Searched refs:outputInts1 (Results 1 – 1 of 1) sorted by relevance
| /external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmInstructionTests.cpp | 1489 vector<deInt32> outputInts1 (numElements, 0); in createSpecConstantGroup() local
1534 outputInts1[ndx] = inputInts[ndx] + 42; in createSpecConstantGroup()
1544 … " %i32 0", "%i32", "IAdd %sc_0 %sc_1", 62, -20, addScToInput, outputInts1)); in createSpecConstantGroup()
1545 … " %i32 0", "%i32", "ISub %sc_0 %sc_1", 100, 58, addScToInput, outputInts1)); in createSpecConstantGroup()
1546 … " %i32 0", "%i32", "IMul %sc_0 %sc_1", -2, -21, addScToInput, outputInts1)); in createSpecConstantGroup()
1547 …" %i32 0", "%i32", "SDiv %sc_0 %sc_1", -126, -3, addScToInput, outputInts1)); in createSpecConstantGroup()
1548 … " %i32 0", "%i32", "UDiv %sc_0 %sc_1", 126, 3, addScToInput, outputInts1)); in createSpecConstantGroup()
1551 … " %i32 0", "%i32", "UMod %sc_0 %sc_1", 342, 50, addScToInput, outputInts1)); in createSpecConstantGroup()
1552 … " %i32 0", "%i32", "BitwiseAnd %sc_0 %sc_1", 42, 63, addScToInput, outputInts1)); in createSpecConstantGroup()
1553 … " %i32 0", "%i32", "BitwiseOr %sc_0 %sc_1", 34, 8, addScToInput, outputInts1)); in createSpecConstantGroup()
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