Searched refs:pmull (Results 1 – 25 of 36) sorted by relevance
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32 pmull v0.1q,v20.1d,v20.1d35 pmull v1.1q,v16.1d,v16.1d41 pmull v18.1q,v0.1d,v19.1d //1st phase48 pmull v0.1q,v0.1d,v19.1d73 pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo76 pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)82 pmull v18.1q,v0.1d,v19.1d //1st phase of reduction89 pmull v0.1q,v0.1d,v19.1d141 pmull v4.1q,v20.1d,v7.1d //H·Ii+1150 pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo[all …]
31 .byte 0xa8,0x0e,0xa8,0xf2 @ pmull q0,q12,q1234 .byte 0xa0,0x2e,0xa0,0xf2 @ pmull q1,q8,q840 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase47 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q1172 .byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo75 .byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)81 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction88 .byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11141 .byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1150 .byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo[all …]
3 pmull v8.8h, v8.8b, v8.8b label5 pmull v8.1q, v8.1d, v8.1d label12 pmull v8.8H, v8.8B, v8.8B label14 pmull v8.1Q, v8.1D, v8.1D label
15 pmull v0.1q, v1.1d, v2.1d
285 pmull v0.8h, v1.8b, v2.8b286 pmull v0.1q, v1.1d, v2.1d
1931 pmull.8h v0, v0, v01933 pmull.1q v2, v3, v41935 pmull v2.1q, v3.1d, v4.1d1938 ; CHECK: pmull.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x0e]1940 ; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]1942 ; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]2084 ; pmull verbose mode aliases2085 pmull v8.8h, v8.8b, v8.8b2087 pmull v8.1q, v8.1d, v8.1d2089 ; CHECK: pmull.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x0e][all …]
2594 pmull v0.8h, v1.8h, v2.8b2600 pmull v0.1q, v1.2d, v2.2d2607 pmull v0.4s, v1.4h, v2.4h2608 pmull v0.2d, v1.2s, v2.2s
8 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
9 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…20 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…30 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…40 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…52 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…63 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…75 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…89 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %pas…102 …%res = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zero…105 declare <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)[all …]
428 %2 = call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %a, x86_mmx %b) nounwind readnone431 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone
2393 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2404 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2414 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2424 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2436 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2447 …%res = call <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16> %a, <32 x i16> %b, <32 x i16> …2451 declare <32 x i16> @llvm.x86.avx512.mask.pmull.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)2458 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zero…2469 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> %pas…2479 …%res = call <8 x i16> @llvm.x86.avx512.mask.pmull.w.128(<8 x i16> %a, <8 x i16> %b, <8 x i16> zero…[all …]
600 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone610 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind625 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
2584 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2595 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2605 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2615 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2627 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2638 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2650 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2664 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2677 …%res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> …2681 declare <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
257 …%tmp52 = tail call x86_mmx @llvm.x86.mmx.pmull.w( x86_mmx %tmp45, x86_mmx %tmp51 ) ; <x86_mmx> [#…305 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx)
555 declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone564 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind578 %2 = tail call x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind
112 ;CHECK: pmull.8h115 %tmp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)119 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone1829 …%res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) no…1841 …%res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) …2015 ; CHECK: pmull.1q
3 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)1791 ; CHECK: pmull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b1793 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %a, <8 x i8> %b)1803 …%vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %shuffle.i.i, <8 x i8> %s…1809 ; CHECK: pmull {{v[0-9]+}}.1q, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d
2204 # CHECK: pmull.8h v0, v0, v02206 # CHECK: pmull.1q v0, v0, v0
2668 V(pmull) \
2355 void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2161 V(pmull, Pmull) \
3520 pmull(vf_l, rd, rn, rm); in VisitNEON3Different()
4202 DEFINE_TEST_NEON_3DIFF_LONG_8H(pmull, Basic)
2842 void pmull(const VRegister& vd,
258 x86_mmx_pmull_w, // llvm.x86.mmx.pmull.w785 "llvm.x86.mmx.pmull.w",2350 return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"6250 case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w7582 case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w