Home
last modified time | relevance | path

Searched refs:q16 (Results 1 – 8 of 8) sorted by relevance

/external/gemmlowp/internal/
Doutput_neon.h160 int16x8_t q16 = vcombine_s16(vqmovn_s32(input), vdup_n_s16(0));
161 return vqmovun_s16(q16);
181 int16x8_t q16[2];
183 q16[i] = vcombine_s16(vqmovn_s32(input.data.val[2 * i]),
186 return vcombine_u8(vqmovun_s16(q16[0]), vqmovun_s16(q16[1]));
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc2968 ASSERT_EQUAL_128(0, 0x14131211, q16); in TEST()
3020 ASSERT_EQUAL_128(0, 0x0a09080706050403, q16); in TEST()
3083 ASSERT_EQUAL_128(0, 0x0a09080706050403, q16); in TEST()
3136 ASSERT_EQUAL_128(0x1211100f0e0d0c0b, 0x0a09080706050403, q16); in TEST()
3188 ASSERT_EQUAL_128(0x1211100f0e0d0c0b, 0x0a09080706050403, q16); in TEST()
3333 ASSERT_EQUAL_128(0, 0x0e0d0c0b06050403, q16); in TEST()
3378 ASSERT_EQUAL_128(0x1e1d1c1b16151413, 0x0e0d0c0b06050403, q16); in TEST()
3418 ASSERT_EQUAL_128(0x1e1d1c1b16151413, 0x0e0d0c0b06050403, q16); in TEST()
3932 __ Ldr(q16, MemOperand(x5, 16, PostIndex)); in TEST()
3966 ASSERT_EQUAL_128(0x1f1e1d1c1b1a1918, 0x0302151413121110, q16); in TEST()
[all …]
Dtest-disasm-aarch64.cc1223 COMPARE(ldr(q16, MemOperand(x17, 65520)), "ldr q16, [x17, #65520]"); in TEST()
1269 COMPARE(ldr(q16, MemOperand(x17, -256, PreIndex)), "ldr q16, [x17, #-256]!"); in TEST()
1316 COMPARE(ldr(q16, MemOperand(x17, -256, PostIndex)), "ldr q16, [x17], #-256"); in TEST()
/external/llvm/test/CodeGen/AArch64/
Darm64-spill.ll12 …,~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q1…
/external/pcre/dist2/src/
Dpcre2test.c5547 uint16_t *q16 = NULL; in process_data() local
5854 *q16++ = 0xD800 | (c >> 10); in process_data()
5855 *q16++ = 0xDC00 | (c & 0x3ff); in process_data()
5858 *q16++ = c; in process_data()
5870 *q16++ = c; in process_data()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td371 def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s2640 ldr q16, [x24, w8, uxtw #4]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt2632 # CHECK: ldr q16, [x24, w8, uxtw #4]