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/external/valgrind/none/tests/arm/
Dv6media.c152 TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
153 TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
154 TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
155 TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
156 TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); in main()
157 TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); in main()
161 TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
162 TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
163 TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
164 TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
[all …]
Dv6intThumb.c403 TESTINST2("mov r0, r1", 1, r0, r1, 0); in old_main()
404 TESTINST2("cpy r0, r1", 1, r0, r1, 0); in old_main()
405 TESTINST2("mov r0, #0", 0, r0, r1, 0); in old_main()
406 TESTINST2("mov r0, #1", 0, r0, r1, 0); in old_main()
408 TESTINST2("movs r0, r1", 1, r0, r1, cv); in old_main()
409 TESTINST2("movs r0, r1", 0, r0, r1, cv); in old_main()
410 TESTINST2("movs r0, r1", 0x80000000, r0, r1, cv); in old_main()
411 TESTINST2("movs r0, #0", 0, r0, r1, cv); in old_main()
412 TESTINST2("movs r0, #1", 0, r0, r1, cv); in old_main()
416 TESTINST2("mvn r0, r1", 1, r0, r1, 0); in old_main()
[all …]
Dv6intARM.c144 TESTINST2("mov r0, r1", 1, r0, r1, 0); in main()
145 TESTINST2("cpy r0, r1", 1, r0, r1, 0); in main()
146 TESTINST2("mov r0, #0", 0, r0, r1, 0); in main()
147 TESTINST2("mov r0, #1", 0, r0, r1, 0); in main()
149 TESTINST2("movs r0, r1", 1, r0, r1, c); in main()
150 TESTINST2("movs r0, r1", 0, r0, r1, c); in main()
151 TESTINST2("movs r0, r1", 0x80000000, r0, r1, c); in main()
152 TESTINST2("movs r0, #0", 0, r0, r1, c); in main()
153 TESTINST2("movs r0, #1", 0, r0, r1, c); in main()
157 TESTINST2("mvn r0, r1", 1, r0, r1, 0); in main()
[all …]
/external/valgrind/none/tests/s390x/
Dopcodes.h19 #define RIL_RI(op1,r1,op2,i2) \ argument
20 ".short 0x" #op1 #r1 #op2 "\n\t" \
22 #define RIE_RRI0(op1,r1,r3,i2,u0,op2) \ argument
23 ".short 0x" #op1 #r1 #r3 "\n\t" \
25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
29 #define RXY_RRRD(op1,r1,x2,b2,dl2,dh2,op2) \ argument
30 ".short 0x" #op1 #r1 #x2 "\n\t" \
32 #define RIL_RU(op1,r1,op2,i2) \ argument
33 ".short 0x" #op1 #r1 #op2 "\n\t" \
35 #define RIL_RP(op1,r1,op2,i2) \ argument
[all …]
Drxsbg.stdout.exp1 RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0)
2 RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
3 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
4 RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0)
5 RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
6 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
7 RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1)
8 RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1)
9 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1)
10 RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0)
[all …]
/external/linux-kselftest/tools/testing/selftests/powerpc/pmu/ebb/
Dbusy_loop.S11 stdu %r1, -168(%r1)
12 std r14, 160(%r1)
13 std r15, 152(%r1)
14 std r16, 144(%r1)
15 std r17, 136(%r1)
16 std r18, 128(%r1)
17 std r19, 120(%r1)
18 std r20, 112(%r1)
19 std r21, 104(%r1)
20 std r22, 96(%r1)
[all …]
/external/llvm/test/MC/ARM/
Dthumb2-narrow-dp.ll17 ADDS r1, r1, #8 // T2
18 // CHECK: adds r1, #8 @ encoding: [0x08,0x31]
19 ADDS.W r1, r1, #8 // .w => T3
20 // CHECK: adds.w r1, r1, #8 @ encoding: [0x11,0xf1,0x08,0x01]
30 ADDEQ r1, r1, #8 // T2
31 // CHECK: addeq r1, #8 @ encoding: [0x08,0x31]
39 ADDSEQ r1, r1, #8 // T3
40 // CHECK: addseq.w r1, r1, #8 @ encoding: [0x11,0xf1,0x08,0x01]
43 ADDS r0, r2, r1 // ADDS has T1 narrow 3 operand
44 // CHECK: adds r0, r2, r1 @ encoding: [0x50,0x18]
[all …]
Darm_addrmode2.s4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
8 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
10 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
11 @ CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
12 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
[all …]
Dthumbv8m.s29 uxtab16 r0, r1, r2
53 sdiv r1, r2, r3
56 udiv r1, r2, r3
64 ldrex r1, [r2, #4]
67 ldrexb r1, [r2]
70 ldrexh r1, [r2]
74 ldrexd r0, r1, [r2]
77 strex r1, r2, [r3, #4]
80 strexb r1, r2, [r3]
83 strexh r1, r2, [r3]
[all …]
Dthumb_rewrites.s4 adds r1, r1, #3
5 @ CHECK: adds r1, r1, #3 @ encoding: [0xc9,0x1c]
7 adds r1, #3
8 @ CHECK: adds r1, #3 @ encoding: [0x03,0x31]
19 add r1, r8, r1
20 @ CHECK: add r1, r8 @ encoding: [0x41,0x44]
38 add r0, r0, r1
39 @ CHECK: add r0, r1 @ encoding: [0x08,0x44]
59 ands r0, r1, r0
60 @ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
[all …]
Dmul-v4.s5 @ ARMV4: mul r0, r1, r2 @ encoding: [0x91,0x02,0x00,0xe0]
6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
7 @ ARMV4: mulne r0, r1, r2 @ encoding: [0x91,0x02,0x00,0x10]
8 @ ARMV4: mulseq r0, r1, r2 @ encoding: [0x91,0x02,0x10,0x00]
9 mul r0, r1, r2
10 muls r0, r1, r2
11 mulne r0, r1, r2
12 mulseq r0, r1, r2
14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
15 @ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dsvol.ll10 ; CHECK: swi r3, r1
11 ; CHECK: swi r4, r1
12 ; CHECK: swi r5, r1
13 ; CHECK: swi r6, r1
14 ; CHECK: swi r7, r1
15 ; CHECK: swi r8, r1
16 ; CHECK: swi r9, r1
17 ; CHECK: swi r10, r1
18 ; CHECK: swi r11, r1
19 ; CHECK: swi r12, r1
[all …]
/external/libcxx/test/std/utilities/function.objects/refwrap/refwrap.invoke/
Dinvoke.pass.cpp48 std::reference_wrapper<void (int)> r1(f_void_1); in test_void_1() local
50 r1(i); in test_void_1()
57 std::reference_wrapper<void (*)(int)> r1(fp); in test_void_1() local
59 r1(i); in test_void_1()
66 std::reference_wrapper<A_void_1> r1(a0); in test_void_1() local
68 r1(i); in test_void_1()
75 std::reference_wrapper<void (A_void_1::*)()> r1(fp); in test_void_1() local
77 r1(a); in test_void_1()
81 r1(ap); in test_void_1()
88 std::reference_wrapper<void (A_void_1::*)() const> r1(fp); in test_void_1() local
[all …]
/external/v8/src/s390/
Dassembler-s390.cc199 const Register kRegisters[] = {r0, r1, r2, r3, r4, r5, r6, r7, in ToRegister()
500 void Assembler::load_label_offset(Register r1, Label* L) { in load_label_offset() argument
520 llilf(r1, Operand(constant)); in load_label_offset()
534 void Assembler::stm(Register r1, Register r2, const MemOperand& src) { in stm() argument
535 rs_form(STM, r1, r2, src.rb(), src.offset()); in stm()
539 void Assembler::stmy(Register r1, Register r2, const MemOperand& src) { in stmy() argument
540 rsy_form(STMY, r1, r2, src.rb(), src.offset()); in stmy()
544 void Assembler::stmg(Register r1, Register r2, const MemOperand& src) { in stmg() argument
545 rsy_form(STMG, r1, r2, src.rb(), src.offset()); in stmg()
589 void Assembler::name(Register r1, Register r2) { rr_form(op, r1, r2); }
[all …]
Dassembler-s390.h82 V(r0) V(r1) V(r2) V(r3) V(r4) V(r5) V(r6) V(r7) \
185 const Register kLithiumScratch = r1; // lithium scratch.
443 void load_label_offset(Register r1, Label* L);
617 iihf(r1, Operand(hi_32)); in breakpoint()
618 iilf(r1, Operand(lo_32)); in breakpoint()
620 iilf(r1, Operand(reinterpret_cast<uint32_t>(&v8::base::OS::DebugBreak))); in breakpoint()
622 basr(r14, r1); in breakpoint()
632 #define RR_FORM(name) void name(Register r1, Register r2)
637 void name(Register r1, Register x2, Register b2, Disp d2); \
638 void name(Register r1, const MemOperand& opnd)
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-good-z196.s199 #CHECK: chf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xcd]
201 #CHECK: chf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xcd]
202 #CHECK: chf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xcd]
210 chf %r0, 0(%r1)
212 chf %r0, 524287(%r1,%r15)
213 chf %r0, 524287(%r15,%r1)
319 #CHECK: clhf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xcf]
321 #CHECK: clhf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xcf]
322 #CHECK: clhf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xcf]
330 clhf %r0, 0(%r1)
[all …]
/external/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.inv/
Dinvoke.pass.cpp39 std::function<int ()> r1(f_int_0); in test_int_0() local
40 assert(r1() == 3); in test_int_0()
45 std::function<int ()> r1(fp); in test_int_0() local
46 assert(r1() == 3); in test_int_0()
51 std::function<int ()> r1(a0); in test_int_0() local
52 assert(r1() == 4); in test_int_0()
75 std::function<void ()> r1(f_void_0); in test_void_0() local
76 r1(); in test_void_0()
83 std::function<void ()> r1(fp); in test_void_0() local
84 r1(); in test_void_0()
[all …]
/external/vixl/test/aarch32/
Dtest-disasm-a32.cc399 masm.Add(r0, r0, r1); in TEST_T32()
413 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n"); in TEST()
420 COMPARE_A32(Orn(r0, r1, 1), in TEST()
429 COMPARE_BOTH(Orn(r0, r1, 0x00ffffff), "orr r0, r1, #0xff000000\n"); in TEST()
430 COMPARE_BOTH(Orn(r0, r1, 0xff00ffff), "orr r0, r1, #0xff0000\n"); in TEST()
431 COMPARE_BOTH(Orns(r0, r1, 0x00ffffff), "orrs r0, r1, #0xff000000\n"); in TEST()
433 COMPARE_A32(Orns(r0, r1, 0xabcd2345), in TEST()
438 COMPARE_T32(Orn(r0, r1, 0xabcd2345), in TEST()
447 COMPARE_A32(Orn(r0, r1, r2), in TEST()
451 COMPARE_A32(Orn(r0, r0, r1), in TEST()
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc96 {{eq, r0, r1, r0}, true, eq, "eq r0 r1 r0", "eq_r0_r1_r0"},
103 {{eq, r1, r0, r1}, true, eq, "eq r1 r0 r1", "eq_r1_r0_r1"},
104 {{eq, r1, r1, r1}, true, eq, "eq r1 r1 r1", "eq_r1_r1_r1"},
105 {{eq, r1, r2, r1}, true, eq, "eq r1 r2 r1", "eq_r1_r2_r1"},
106 {{eq, r1, r3, r1}, true, eq, "eq r1 r3 r1", "eq_r1_r3_r1"},
107 {{eq, r1, r4, r1}, true, eq, "eq r1 r4 r1", "eq_r1_r4_r1"},
108 {{eq, r1, r5, r1}, true, eq, "eq r1 r5 r1", "eq_r1_r5_r1"},
109 {{eq, r1, r6, r1}, true, eq, "eq r1 r6 r1", "eq_r1_r6_r1"},
110 {{eq, r1, r7, r1}, true, eq, "eq r1 r7 r1", "eq_r1_r7_r1"},
112 {{eq, r2, r1, r2}, true, eq, "eq r2 r1 r2", "eq_r2_r1_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
98 {{gt, r3, r1, r0}, true, gt, "gt r3 r1 r0", "gt_r3_r1_r0"},
101 {{hi, r1, r0, r0}, true, hi, "hi r1 r0 r0", "hi_r1_r0_r0"},
102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
104 {{ne, r1, r7, r0}, true, ne, "ne r1 r7 r0", "ne_r1_r7_r0"},
107 {{ne, r5, r1, r0}, true, ne, "ne r5 r1 r0", "ne_r5_r1_r0"},
109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"},
110 {{cs, r1, r4, r7}, true, cs, "cs r1 r4 r7", "cs_r1_r4_r7"},
112 {{ne, r1, r7, r1}, true, ne, "ne r1 r7 r1", "ne_r1_r7_r1"},
115 {{ls, r3, r3, r1}, true, ls, "ls r3 r3 r1", "ls_r3_r3_r1"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
107 {{gt, r7, r7, r1}, true, gt, "gt r7 r7 r1", "gt_r7_r7_r1"},
115 {{cc, r1, r1, r0}, true, cc, "cc r1 r1 r0", "cc_r1_r1_r0"},
116 {{cc, r1, r1, r1}, true, cc, "cc r1 r1 r1", "cc_r1_r1_r1"},
127 {{vs, r1, r1, r5}, true, vs, "vs r1 r1 r5", "vs_r1_r1_r5"},
140 {{vc, r0, r0, r1}, true, vc, "vc r0 r0 r1", "vc_r0_r0_r1"},
148 {{pl, r5, r5, r1}, true, pl, "pl r5 r5 r1", "pl_r5_r5_r1"},
149 {{mi, r1, r1, r1}, true, mi, "mi r1 r1 r1", "mi_r1_r1_r1"},
155 {{cc, r1, r1, r7}, true, cc, "cc r1 r1 r7", "cc_r1_r1_r7"},
156 {{ls, r0, r0, r1}, true, ls, "ls r0 r0 r1", "ls_r0_r0_r1"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
98 {{gt, r1, r1, LSL, r0}, true, gt, "gt r1 r1 LSL r0", "gt_r1_r1_LSL_r0"},
100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
111 {{vs, r2, r2, LSL, r1}, true, vs, "vs r2 r2 LSL r1", "vs_r2_r2_LSL_r1"},
117 {{eq, r5, r5, LSR, r1}, true, eq, "eq r5 r5 LSR r1", "eq_r5_r5_LSR_r1"},
118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"},
121 {{cc, r1, r1, LSL, r6}, true, cc, "cc r1 r1 LSL r6", "cc_r1_r1_LSL_r6"},
125 {{hi, r1, r1, ASR, r6}, true, hi, "hi r1 r1 ASR r6", "hi_r1_r1_ASR_r6"},
131 {{ls, r1, r1, LSR, r0}, true, ls, "ls r1 r1 LSR r0", "ls_r1_r1_LSR_r0"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Darm_addrmode2.s4 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
6 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
7 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
9 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
10 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
12 @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
13 @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
[all …]
Darm_instructions.s15 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
16 and r1,r2,r3
18 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
19 ands r1,r2,r3
21 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
22 eor r1,r2,r3
24 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
25 eors r1,r2,r3
27 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
28 sub r1,r2,r3
[all …]
/external/eigen/test/
Dblock.cpp15 block_real_only(const MatrixType &m1, Index r1, Index r2, Index c1, Index c2, const Scalar& s1) { in block_real_only() argument
17 VERIFY_IS_APPROX(m1.row(r1).cwiseMax(s1), m1.cwiseMax(s1).row(r1)); in block_real_only()
20 …VERIFY_IS_APPROX(m1.block(r1,c1,r2-r1+1,c2-c1+1).cwiseMin(s1), m1.cwiseMin(s1).block(r1,c1,r2-r1+1… in block_real_only()
21 …VERIFY_IS_APPROX(m1.block(r1,c1,r2-r1+1,c2-c1+1).cwiseMax(s1), m1.cwiseMax(s1).block(r1,c1,r2-r1+1… in block_real_only()
55 Index r1 = internal::random<Index>(0,rows-1); in block() local
56 Index r2 = internal::random<Index>(r1,rows-1); in block()
60 block_real_only(m1, r1, r2, c1, c1, s1); in block()
66 m1.row(r1) += s1 * m1_copy.row(r2); in block()
67 VERIFY_IS_APPROX(m1.row(r1), m1_copy.row(r1) + s1 * m1_copy.row(r2)); in block()
69 m1.row(r1).row(0) += s1 * m1_copy.row(r2); in block()
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