| /external/boringssl/mac-x86_64/crypto/sha/ |
| D | sha512-x86_64.S | 24 pushq %r12
53 movq 0(%rsi),%r12
56 bswapq %r12
64 movq %r12,0(%rsp)
69 addq %r11,%r12
74 addq %r15,%r12
77 addq (%rbp),%r12
86 addq %r13,%r12
89 addq %r12,%rdx
90 addq %r12,%r11
[all …]
|
| /external/boringssl/linux-x86_64/crypto/sha/ |
| D | sha512-x86_64.S | 25 pushq %r12
54 movq 0(%rsi),%r12
57 bswapq %r12
65 movq %r12,0(%rsp)
70 addq %r11,%r12
75 addq %r15,%r12
78 addq (%rbp),%r12
87 addq %r13,%r12
90 addq %r12,%rdx
91 addq %r12,%r11
[all …]
|
| /external/boringssl/win-x86_64/crypto/sha/ |
| D | sha512-x86_64.asm | 36 push r12
65 mov r12,QWORD[rsi]
68 bswap r12
76 mov QWORD[rsp],r12
81 add r12,r11
86 add r12,r15
89 add r12,QWORD[rbp]
98 add r12,r13
101 add rdx,r12
102 add r11,r12
[all …]
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-6xx.s | 8 mfibatu %r12, 0
11 mfibatl %r12, 0
14 mfibatu %r12, 1
17 mfibatl %r12, 1
20 mfibatu %r12, 2
23 mfibatl %r12, 2
26 mfibatu %r12, 3
29 mfibatl %r12, 3
32 mtibatu 0, %r12
35 mtibatl 0, %r12
[all …]
|
| /external/boringssl/linux-arm/crypto/aes/ |
| D | aes-armv4.S | 172 stmdb sp!,{r1,r4-r12,lr}
178 mov r12,r0 @ inp
181 ldrb r0,[r12,#3] @ load input data in endian-neutral
182 ldrb r4,[r12,#2] @ manner...
183 ldrb r5,[r12,#1]
184 ldrb r6,[r12,#0]
186 ldrb r1,[r12,#7]
188 ldrb r4,[r12,#6]
190 ldrb r5,[r12,#5]
191 ldrb r6,[r12,#4]
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-rd-rn-rm-t32.cc | 100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
115 {{r12, r12, r9}, false, al, "r12 r12 r9", "r12_r12_r9"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
122 {{r12, r8, r4}, false, al, "r12 r8 r4", "r12_r8_r4"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
135 {{r8, r12, r13}, false, al, "r8 r12 r13", "r8_r12_r13"},
[all …]
|
| D | test-assembler-rd-rn-rm-a32.cc | 100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
115 {{r12, r12, r9}, false, al, "r12 r12 r9", "r12_r12_r9"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
122 {{r12, r8, r4}, false, al, "r12 r8 r4", "r12_r8_r4"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
135 {{r8, r12, r13}, false, al, "r8 r12 r13", "r8_r12_r13"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-a32.cc | 94 const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
95 {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
102 {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
109 {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
137 {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
141 {{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-t32.cc | 94 const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
95 {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
102 {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
109 {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
137 {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
141 {{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 116 const TestData kTests[] = {{{al, r6, r8, r10, LSL, r12},
141 {{cs, r12, r9, r12, LSR, r0},
146 {{mi, r12, r3, r13, ASR, r3},
166 {{vc, r0, r5, r14, ASR, r12},
236 {{lt, r4, r6, r12, LSL, r8},
241 {{cs, r12, r3, r3, ASR, r2},
271 {{lt, r5, r8, r12, ROR, r0},
301 {{mi, r6, r12, r4, ASR, r9},
306 {{cs, r12, r0, r12, LSL, r9},
336 {{vc, r11, r9, r14, LSR, r12},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc | 103 {{hi, r12, r12, r2}, true, hi, "hi r12 r12 r2", "hi_r12_r12_r2"},
107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"},
113 {{gt, r7, r7, r12}, true, gt, "gt r7 r7 r12", "gt_r7_r7_r12"},
116 {{ge, r12, r12, r2}, true, ge, "ge r12 r12 r2", "ge_r12_r12_r2"},
119 {{gt, r12, r12, r5}, true, gt, "gt r12 r12 r5", "gt_r12_r12_r5"},
125 {{ge, r3, r3, r12}, true, ge, "ge r3 r3 r12", "ge_r3_r3_r12"},
132 {{cc, r12, r12, r0}, true, cc, "cc r12 r12 r0", "cc_r12_r12_r0"},
153 {{mi, r2, r2, r12}, true, mi, "mi r2 r2 r12", "mi_r2_r2_r12"},
155 {{cc, r5, r5, r12}, true, cc, "cc r5 r5 r12", "cc_r5_r5_r12"},
160 {{vc, r9, r9, r12}, true, vc, "vc r9 r9 r12", "vc_r9_r9_r12"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-t32-in-it-block.cc | 108 {{eq, r0, r12}, true, eq, "eq r0 r12", "eq_r0_r12"},
123 {{eq, r1, r12}, true, eq, "eq r1 r12", "eq_r1_r12"},
138 {{eq, r2, r12}, true, eq, "eq r2 r12", "eq_r2_r12"},
153 {{eq, r3, r12}, true, eq, "eq r3 r12", "eq_r3_r12"},
168 {{eq, r4, r12}, true, eq, "eq r4 r12", "eq_r4_r12"},
183 {{eq, r5, r12}, true, eq, "eq r5 r12", "eq_r5_r12"},
198 {{eq, r6, r12}, true, eq, "eq r6 r12", "eq_r6_r12"},
213 {{eq, r7, r12}, true, eq, "eq r7 r12", "eq_r7_r12"},
228 {{eq, r8, r12}, true, eq, "eq r8 r12", "eq_r8_r12"},
243 {{eq, r9, r12}, true, eq, "eq r9 r12", "eq_r9_r12"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 132 {{cc, r12, r9, r11, ROR, 16},
172 {{ls, r12, r8, r2, ROR, 24},
187 {{ge, r0, r4, r12, ROR, 0},
212 {{eq, r4, r12, r2, ROR, 0},
237 {{le, r12, r2, r2, ROR, 16},
302 {{eq, r11, r12, r1, ROR, 16},
307 {{pl, r2, r12, r9, ROR, 16},
362 {{pl, r12, r8, r4, ROR, 16},
387 {{lt, r3, r12, r3, ROR, 24},
397 {{vc, r12, r4, r0, ROR, 0},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32.cc | 129 {{{al, r12, r9, r11}, false, al, "al r12 r9 r11", "al_r12_r9_r11"},
131 {{al, r2, r0, r12}, false, al, "al r2 r0 r12", "al_r2_r0_r12"},
137 {{al, r14, r12, r14}, false, al, "al r14 r12 r14", "al_r14_r12_r14"},
153 {{al, r12, r5, r2}, false, al, "al r12 r5 r2", "al_r12_r5_r2"},
163 {{al, r14, r12, r7}, false, al, "al r14 r12 r7", "al_r14_r12_r7"},
166 {{al, r12, r4, r4}, false, al, "al r12 r4 r4", "al_r12_r4_r4"},
171 {{al, r2, r12, r1}, false, al, "al r2 r12 r1", "al_r2_r12_r1"},
175 {{al, r12, r5, r1}, false, al, "al r12 r5 r1", "al_r12_r5_r1"},
179 {{al, r0, r11, r12}, false, al, "al r0 r11 r12", "al_r0_r11_r12"},
182 {{al, r2, r12, r9}, false, al, "al r2 r12 r9", "al_r2_r12_r9"},
[all …]
|
| D | test-assembler-cond-rd-rn-a32.cc | 101 {{{cs, r12, r1}, false, al, "cs r12 r1", "cs_r12_r1"},
102 {{hi, r6, r12}, false, al, "hi r6 r12", "hi_r6_r12"},
109 {{pl, r4, r12}, false, al, "pl r4 r12", "pl_r4_r12"},
110 {{gt, r12, r12}, false, al, "gt r12 r12", "gt_r12_r12"},
116 {{al, r3, r12}, false, al, "al r3 r12", "al_r3_r12"},
137 {{ge, r12, r2}, false, al, "ge r12 r2", "ge_r12_r2"},
142 {{lt, r13, r12}, false, al, "lt r13 r12", "lt_r13_r12"},
144 {{mi, r12, r14}, false, al, "mi r12 r14", "mi_r12_r14"},
148 {{le, r10, r12}, false, al, "le r10 r12", "le_r10_r12"},
152 {{lt, r7, r12}, false, al, "lt r7 r12", "lt_r7_r12"},
[all …]
|
| /external/tremolo/Tremolo/ |
| D | mdctLARM.s | 61 LDMDB r2!,{r5,r6,r7,r12}
66 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
68 MOV r14,r12,ASR #15
70 EORNE r12,r4, r14,ASR #31
71 STRH r12,[r0], r3
121 LDR r12,[r2],#8
126 RSB r12,r12,#0
131 MOV r12, r12,ASR #9 @ r12= (-*l)>>9
136 MOV r14,r12,ASR #15
138 EORNE r12,r4, r14,ASR #31
[all …]
|
| D | mdctARM.s | 63 LDMDB r2!,{r5,r6,r7,r12}
68 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
70 MOV r14,r12,ASR #15
72 EORNE r12,r4, r14,ASR #31
73 STRH r12,[r0], r3
123 LDR r12,[r2],#8
128 RSB r12,r12,#0
133 MOV r12, r12,ASR #9 @ r12= (-*l)>>9
138 MOV r14,r12,ASR #15
140 EORNE r12,r4, r14,ASR #31
[all …]
|
| D | bitwiseARM.s | 46 LDMIA r0,{r2,r3,r12}
49 @ r12= bitsLeftInWord
54 RSB r14,r12,#32 @ r14= 32-bitsLeftInWord
55 SUBS r12,r12,r1 @ r12= bitsLeftInWord -= bits
58 ADDLE r12,r12,#32 @ r12= bitsLeftInWord += 32
71 @ r12 = bitsLeftInWord
72 RSB r14,r12,#32 @ r14= 32-bitsLeftInWord
75 BEQ look_next_segment @ r10= r12 = 0, if we branch
76 CMP r12,r10 @ If bitsLeftInWord < bitsLeftInSeg
82 ORRLT r10,r10,r6,LSL r12 @ r10= first bitsLeftInSeg bits+crap
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_chroma_horz.s | 99 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
105 add r12,r0,r6 @*pu1_ref[four_nt]
115 sub r12,r12,#16 @move to 16th value pointer
119 vld1.16 {q0},[r12] @load 16 values. d1[7] will have the 1st value.
120 sub r12,r12,#16
121 vld1.16 {q5},[r12] @load 16 values. d1[7] will have the 1st value.
177 sub r12,r12,#16 @move to 16th value pointer
190 ldmfd sp!,{r4-r12,r15} @reload the registers from sp
194 ldrb lr,[r12],#1 @pu1_ref[two_nt]
195 @vld1.8 {q15},[r12] @pu1_ref[two_nt + 1 + col]
[all …]
|
| D | ihevc_inter_pred_chroma_horz.s | 108 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
121 sub r12,r0,#2 @pu1_src - 2
123 add r4,r12,r2 @pu1_src_tmp2_8 = pu1_src + src_strd
152 add r4,r12,r2
154 and r0, r12, #31
156 pld [r12, r2, lsl #1]
161 vld1.u32 {q0},[r12],r11 @vector load pu1_src
163 vld1.u32 {q1},[r12],r11 @vector load pu1_src
165 vld1.u32 {q2},[r12],r11 @vector load pu1_src
167 vld1.u32 {q3},[r12],r9 @vector load pu1_src
[all …]
|
| D | ihevc_inter_pred_chroma_horz_w16out.s | 107 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
124 sub r12,r0,#2 @pu1_src - 2
126 add r4,r12,r2 @pu1_src_tmp2_8 = pu1_src + src_strd
166 add r4,r12,r2
169 and r0, r12, #31
170 pld [r12, r2, lsl #1]
178 vld1.u32 {q0},[r12],r11 @vector load pu1_src
181 vld1.u32 {q1},[r12],r11 @vector load pu1_src
184 vld1.u32 {q2},[r12],r11 @vector load pu1_src
187 vld1.u32 {q3},[r12],r9 @vector load pu1_src
[all …]
|
| D | ihevc_inter_pred_luma_horz_w16out.s | 108 @r12 - src_ptr1
124 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
136 sub r12,r0,#3 @pu1_src - 3
138 add r4,r12,r2 @pu1_src_tmp2_8 = pu1_src + src_strd
185 sub r12,r0,#3 @pu1_src - 3
189 add r12,#8
196 add r4,r12,r2 @pu1_src + src_strd
202 vld1.u32 {d0},[r12],r11 @vector load pu1_src
203 vld1.u32 {d1},[r12],r11
204 vld1.u32 {d2},[r12],r11
[all …]
|
| D | ihevc_intra_pred_luma_horz.s | 99 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
106 add r12,r0,r6 @*pu1_ref[two_nt]
115 sub r12,r12,#16 @move to 16th value pointer
119 vld1.8 {q0},[r12] @load 16 values. d1[7] will have the 1st value.
175 sub r12,r12,#16 @move to 16th value pointer
188 ldmfd sp!,{r4-r12,r15} @reload the registers from sp
192 ldrb lr,[r12],#1 @pu1_ref[two_nt]
193 vld1.8 {q15},[r12] @pu1_ref[two_nt + 1 + col]
196 sub r12,r12,#17
197 vld1.8 {q0},[r12]
[all …]
|
| /external/boringssl/linux-arm/crypto/chacha/ |
| D | chacha-armv4.S | 34 ldr r12,[sp,#0] @ pull pointer to counter and nonce
59 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
75 str r12, [sp,#4*(32+1)] @ save inp
79 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
90 mov r12,r12,ror#16
93 eor r12,r12,r0,ror#16
95 add r8,r8,r12
102 mov r12,r12,ror#24
105 eor r12,r12,r0,ror#24
107 add r8,r8,r12
[all …]
|
| /external/llvm/test/MC/X86/ |
| D | x86_64-bmi-encoding.s | 69 bextrq %r12, (%rax), %r10
73 bextrq %r12, %r11, %r10
85 bzhiq %r12, (%rax), %r10
89 bzhiq %r12, %r11, %r10
101 pextq %r12, %r11, %r10
117 pdepq %r12, %r11, %r10
133 mulxq %r12, %r11, %r10
149 rorxq $1, %r12, %r10
165 shlxq %r12, (%rax), %r10
169 shlxq %r12, %r11, %r10
[all …]
|