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/external/swiftshader/third_party/LLVM/test/MC/ARM/
Darm-arithmetic-aliases.s6 sub r2, r2, #6
7 sub r2, #6
8 sub r2, r2, r3
9 sub r2, r3
11 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
12 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
16 add r2, r2, #6
17 add r2, #6
[all …]
Dbasic-thumb2-instructions.s22 adc r1, r2, #255
27 adc r4, r2, #0x7f800000
28 adc r4, r2, #0x00000680
32 @ CHECK: adc r1, r2, #255 @ encoding: [0x42,0xf1,0xff,0x01]
37 @ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44]
38 @ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64]
66 addeq r1, r2, #4
69 add r2, sp, #1024
70 add r2, r8, #0xff00
71 add r2, r3, #257
[all …]
Dbasic-thumb-instructions.s33 adds r1, r2, #3
36 adds r2, #3
37 adds r2, #8
39 @ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
40 @ CHECK: adds r2, #3 @ encoding: [0x03,0x32]
41 @ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
47 adds r1, r2, r3
48 add r2, r8
50 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
51 @ CHECK: add r2, r8 @ encoding: [0x42,0x44]
[all …]
Darm_instructions.s15 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
16 and r1,r2,r3
18 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
19 ands r1,r2,r3
21 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
22 eor r1,r2,r3
24 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
25 eors r1,r2,r3
27 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
28 sub r1,r2,r3
[all …]
Dbasic-arm-instructions.s17 adc r1, r2, #0xf
18 adc r1, r2, #0xf0
19 adc r1, r2, #0xf00
20 adc r1, r2, #0xf000
21 adc r1, r2, #0xf0000
22 adc r1, r2, #0xf00000
23 adc r1, r2, #0xf000000
24 adc r1, r2, #0xf0000000
25 adc r1, r2, #0xf000000f
26 adcs r1, r2, #0xf00
[all …]
/external/llvm/test/MC/ARM/
Darm-arithmetic-aliases.s6 sub r2, r2, #6
7 sub r2, #6
8 sub r2, r2, r3
9 sub r2, r3
11 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
12 @ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2]
13 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
14 @ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0]
16 add r2, r2, #6
17 add r2, #6
[all …]
Dmul-v4.s5 @ ARMV4: mul r0, r1, r2 @ encoding: [0x91,0x02,0x00,0xe0]
6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
7 @ ARMV4: mulne r0, r1, r2 @ encoding: [0x91,0x02,0x00,0x10]
8 @ ARMV4: mulseq r0, r1, r2 @ encoding: [0x91,0x02,0x10,0x00]
9 mul r0, r1, r2
10 muls r0, r1, r2
11 mulne r0, r1, r2
12 mulseq r0, r1, r2
14 @ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
15 @ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
[all …]
Darm_instructions.s22 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
23 and r1,r2,r3
25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
26 ands r1,r2,r3
28 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
29 eor r1,r2,r3
31 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
32 eors r1,r2,r3
34 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
35 sub r1,r2,r3
[all …]
Dbasic-thumb2-instructions.s23 adc r1, r2, #255
28 adc r4, r2, #0x7f800000
29 adc r4, r2, #0x00000680
33 @ CHECK: adc r1, r2, #255 @ encoding: [0x42,0xf1,0xff,0x01]
38 @ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44]
39 @ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64]
67 addeq r1, r2, #4
70 add r2, sp, #1024
71 add r2, r8, #0xff00
72 add r2, r3, #257
[all …]
Dbasic-thumb-instructions.s34 adds r1, r2, #3
37 adds r2, #3
38 adds r2, #8
40 @ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
41 @ CHECK: adds r2, #3 @ encoding: [0x03,0x32]
42 @ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
48 adds r1, r2, r3
49 add r2, r8
51 @ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
52 @ CHECK: add r2, r8 @ encoding: [0x42,0x44]
[all …]
/external/valgrind/none/tests/arm/
Dv6media.c152 TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
153 TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
154 TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
155 TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
156 TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0); in main()
157 TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0); in main()
161 TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
162 TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0); in main()
163 TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0); in main()
164 TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0); in main()
[all …]
Dv6intThumb.c424 TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0); in old_main()
425 TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0); in old_main()
426 TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0); in old_main()
427 TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0); in old_main()
428 TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0); in old_main()
429 TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0); in old_main()
430 TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0); in old_main()
431 TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0); in old_main()
432 TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0); in old_main()
435 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0); in old_main()
[all …]
Dv6intARM.c165 TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
166 TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0); in main()
167 TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0); in main()
168 TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0); in main()
169 TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0); in main()
170 TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0); in main()
171 TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0); in main()
172 TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0); in main()
173 TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0); in main()
176 TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0); in main()
[all …]
/external/valgrind/none/tests/s390x/
Drxsbg.stdout.exp1 RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0)
2 RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
3 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
4 RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0)
5 RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
6 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
7 RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1)
8 RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1)
9 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1)
10 RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0)
[all …]
Dopcodes.h25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
47 #define RRS(op1,r1,r2,b4,d4,m3,u0,op2) \ argument
48 ".short 0x" #op1 #r1 #r2 "\n\t" \
50 #define RIE_RRPU(op1,r1,r2,i4,m3,u0,op2) \ argument
51 ".short 0x" #op1 #r1 #r2 "\n\t" \
53 #define RRE_RR(op,u0,r1,r2) ".long 0x" #op #u0 #r1 #r2 "\n\t" argument
54 #define RRE_RERE(op,r1,r2) ".long 0x" #op "00" #r1 #r2 "\n\t" argument
71 #define RRF_F0FF2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" argument
72 #define RRF_FUFF2(op,r3,m4,r1,r2) ".long 0x" #op #r3 #m4 #r1 #r2 "\n\t" argument
73 #define RRF_UUFR(op,m3,m4,r1,r2) ".long 0x" #op #m3 #m4 #r1 #r2 "\n\t" argument
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc97 {{eq, r0, r2, r0}, true, eq, "eq r0 r2 r0", "eq_r0_r2_r0"},
105 {{eq, r1, r2, r1}, true, eq, "eq r1 r2 r1", "eq_r1_r2_r1"},
111 {{eq, r2, r0, r2}, true, eq, "eq r2 r0 r2", "eq_r2_r0_r2"},
112 {{eq, r2, r1, r2}, true, eq, "eq r2 r1 r2", "eq_r2_r1_r2"},
113 {{eq, r2, r2, r2}, true, eq, "eq r2 r2 r2", "eq_r2_r2_r2"},
114 {{eq, r2, r3, r2}, true, eq, "eq r2 r3 r2", "eq_r2_r3_r2"},
115 {{eq, r2, r4, r2}, true, eq, "eq r2 r4 r2", "eq_r2_r4_r2"},
116 {{eq, r2, r5, r2}, true, eq, "eq r2 r5 r2", "eq_r2_r5_r2"},
117 {{eq, r2, r6, r2}, true, eq, "eq r2 r6 r2", "eq_r2_r6_r2"},
118 {{eq, r2, r7, r2}, true, eq, "eq r2 r7 r2", "eq_r2_r7_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"},
111 {{hi, r6, r0, r2}, true, hi, "hi r6 r0 r2", "hi_r6_r0_r2"},
121 {{lt, r3, r5, r2}, true, lt, "lt r3 r5 r2", "lt_r3_r5_r2"},
126 {{cs, r7, r2, r5}, true, cs, "cs r7 r2 r5", "cs_r7_r2_r5"},
127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"},
129 {{ge, r7, r2, r4}, true, ge, "ge r7 r2 r4", "ge_r7_r2_r4"},
131 {{le, r2, r4, r0}, true, le, "le r2 r4 r0", "le_r2_r4_r0"},
133 {{hi, r0, r0, r2}, true, hi, "hi r0 r0 r2", "hi_r0_r0_r2"},
134 {{eq, r2, r3, r2}, true, eq, "eq r2 r3 r2", "eq_r2_r3_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc108 {{gt, r2, r2, r0}, true, gt, "gt r2 r2 r0", "gt_r2_r2_r0"},
109 {{eq, r5, r5, r2}, true, eq, "eq r5 r5 r2", "eq_r5_r5_r2"},
125 {{le, r2, r2, r7}, true, le, "le r2 r2 r7", "le_r2_r2_r7"},
130 {{cc, r2, r2, r5}, true, cc, "cc r2 r2 r5", "cc_r2_r2_r5"},
132 {{ls, r7, r7, r2}, true, ls, "ls r7 r7 r2", "ls_r7_r7_r2"},
133 {{lt, r0, r0, r2}, true, lt, "lt r0 r0 r2", "lt_r0_r0_r2"},
146 {{ls, r2, r2, r5}, true, ls, "ls r2 r2 r5", "ls_r2_r2_r5"},
151 {{gt, r2, r2, r7}, true, gt, "gt r2 r2 r7", "gt_r2_r2_r7"},
152 {{ge, r2, r2, r5}, true, ge, "ge r2 r2 r5", "ge_r2_r2_r5"},
160 {{le, r2, r2, r5}, true, le, "le r2 r2 r5", "le_r2_r2_r5"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc609 {{al, r2, r2, 0}, false, al, "al r2 r2 0", "al_r2_r2_0"},
610 {{al, r2, r2, 1}, false, al, "al r2 r2 1", "al_r2_r2_1"},
611 {{al, r2, r2, 2}, false, al, "al r2 r2 2", "al_r2_r2_2"},
612 {{al, r2, r2, 3}, false, al, "al r2 r2 3", "al_r2_r2_3"},
613 {{al, r2, r2, 4}, false, al, "al r2 r2 4", "al_r2_r2_4"},
614 {{al, r2, r2, 5}, false, al, "al r2 r2 5", "al_r2_r2_5"},
615 {{al, r2, r2, 6}, false, al, "al r2 r2 6", "al_r2_r2_6"},
616 {{al, r2, r2, 7}, false, al, "al r2 r2 7", "al_r2_r2_7"},
617 {{al, r2, r2, 8}, false, al, "al r2 r2 8", "al_r2_r2_8"},
618 {{al, r2, r2, 9}, false, al, "al r2 r2 9", "al_r2_r2_9"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc98 {{cs, r0, r2, 5}, true, cs, "cs r0 r2 5", "cs_r0_r2_5"},
101 {{cs, r5, r2, 0}, true, cs, "cs r5 r2 0", "cs_r5_r2_0"},
103 {{ls, r2, r0, 5}, true, ls, "ls r2 r0 5", "ls_r2_r0_5"},
109 {{vc, r5, r2, 5}, true, vc, "vc r5 r2 5", "vc_r5_r2_5"},
111 {{cs, r2, r5, 4}, true, cs, "cs r2 r5 4", "cs_r2_r5_4"},
115 {{vc, r1, r2, 0}, true, vc, "vc r1 r2 0", "vc_r1_r2_0"},
119 {{ge, r2, r0, 0}, true, ge, "ge r2 r0 0", "ge_r2_r0_0"},
121 {{lt, r5, r2, 0}, true, lt, "lt r5 r2 0", "lt_r5_r2_0"},
127 {{pl, r5, r2, 2}, true, pl, "pl r5 r2 2", "pl_r5_r2_2"},
128 {{ls, r7, r2, 0}, true, ls, "ls r7 r2 0", "ls_r7_r2_0"},
[all …]
Dtest-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc97 {{eq, r0, r2}, true, eq, "eq r0 r2", "eq_r0_r2"},
105 {{eq, r1, r2}, true, eq, "eq r1 r2", "eq_r1_r2"},
111 {{eq, r2, r0}, true, eq, "eq r2 r0", "eq_r2_r0"},
112 {{eq, r2, r1}, true, eq, "eq r2 r1", "eq_r2_r1"},
113 {{eq, r2, r2}, true, eq, "eq r2 r2", "eq_r2_r2"},
114 {{eq, r2, r3}, true, eq, "eq r2 r3", "eq_r2_r3"},
115 {{eq, r2, r4}, true, eq, "eq r2 r4", "eq_r2_r4"},
116 {{eq, r2, r5}, true, eq, "eq r2 r5", "eq_r2_r5"},
117 {{eq, r2, r6}, true, eq, "eq r2 r6", "eq_r2_r6"},
118 {{eq, r2, r7}, true, eq, "eq r2 r7", "eq_r2_r7"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc97 {{eq, r0, r2, 0}, true, eq, "eq r0 r2 0", "eq_r0_r2_0"},
105 {{eq, r1, r2, 0}, true, eq, "eq r1 r2 0", "eq_r1_r2_0"},
111 {{eq, r2, r0, 0}, true, eq, "eq r2 r0 0", "eq_r2_r0_0"},
112 {{eq, r2, r1, 0}, true, eq, "eq r2 r1 0", "eq_r2_r1_0"},
113 {{eq, r2, r2, 0}, true, eq, "eq r2 r2 0", "eq_r2_r2_0"},
114 {{eq, r2, r3, 0}, true, eq, "eq r2 r3 0", "eq_r2_r3_0"},
115 {{eq, r2, r4, 0}, true, eq, "eq r2 r4 0", "eq_r2_r4_0"},
116 {{eq, r2, r5, 0}, true, eq, "eq r2 r5 0", "eq_r2_r5_0"},
117 {{eq, r2, r6, 0}, true, eq, "eq r2 r6 0", "eq_r2_r6_0"},
118 {{eq, r2, r7, 0}, true, eq, "eq r2 r7 0", "eq_r2_r7_0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc164 {{eq, r2, r2, 248}, true, eq, "eq r2 r2 248", "eq_r2_r2_248"},
165 {{le, r2, r2, 252}, true, le, "le r2 r2 252", "le_r2_r2_252"},
166 {{cc, r2, r2, 93}, true, cc, "cc r2 r2 93", "cc_r2_r2_93"},
174 {{ne, r2, r2, 168}, true, ne, "ne r2 r2 168", "ne_r2_r2_168"},
180 {{ls, r2, r2, 202}, true, ls, "ls r2 r2 202", "ls_r2_r2_202"},
185 {{ls, r2, r2, 21}, true, ls, "ls r2 r2 21", "ls_r2_r2_21"},
186 {{mi, r2, r2, 54}, true, mi, "mi r2 r2 54", "mi_r2_r2_54"},
188 {{pl, r2, r2, 165}, true, pl, "pl r2 r2 165", "pl_r2_r2_165"},
189 {{gt, r2, r2, 154}, true, gt, "gt r2 r2 154", "gt_r2_r2_154"},
195 {{vc, r2, r2, 69}, true, vc, "vc r2 r2 69", "vc_r2_r2_69"},
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dselectcc-02.ll8 ; CHECK: ipm %r2
9 ; CHECK-NEXT: afi %r2, 1879048192
10 ; CHECK-NEXT: sra %r2, 31
20 ; CHECK: ipm %r2
21 ; CHECK-NEXT: xilf %r2, 268435456
22 ; CHECK-NEXT: afi %r2, 1879048192
23 ; CHECK-NEXT: sra %r2, 31
33 ; CHECK: ipm %r2
34 ; CHECK-NEXT: sll %r2, 2
35 ; CHECK-NEXT: sra %r2, 31
[all …]
Dselectcc-01.ll8 ; CHECK: ipm %r2
9 ; CHECK-NEXT: afi %r2, -268435456
10 ; CHECK-NEXT: sra %r2, 31
20 ; CHECK: ipm %r2
21 ; CHECK-NEXT: xilf %r2, 268435456
22 ; CHECK-NEXT: afi %r2, -268435456
23 ; CHECK-NEXT: sra %r2, 31
33 ; CHECK: ipm %r2
34 ; CHECK-NEXT: afi %r2, -536870912
35 ; CHECK-NEXT: sra %r2, 31
[all …]

12345678910>>...75