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/external/vixl/test/aarch32/
Dtest-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc102 {{eq, r0, r7, r0}, true, eq, "eq r0 r7 r0", "eq_r0_r7_r0"},
110 {{eq, r1, r7, r1}, true, eq, "eq r1 r7 r1", "eq_r1_r7_r1"},
118 {{eq, r2, r7, r2}, true, eq, "eq r2 r7 r2", "eq_r2_r7_r2"},
126 {{eq, r3, r7, r3}, true, eq, "eq r3 r7 r3", "eq_r3_r7_r3"},
134 {{eq, r4, r7, r4}, true, eq, "eq r4 r7 r4", "eq_r4_r7_r4"},
142 {{eq, r5, r7, r5}, true, eq, "eq r5 r7 r5", "eq_r5_r7_r5"},
150 {{eq, r6, r7, r6}, true, eq, "eq r6 r7 r6", "eq_r6_r7_r6"},
151 {{eq, r7, r0, r7}, true, eq, "eq r7 r0 r7", "eq_r7_r0_r7"},
152 {{eq, r7, r1, r7}, true, eq, "eq r7 r1 r7", "eq_r7_r1_r7"},
153 {{eq, r7, r2, r7}, true, eq, "eq r7 r2 r7", "eq_r7_r2_r7"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc107 {{gt, r7, r7, r1}, true, gt, "gt r7 r7 r1", "gt_r7_r7_r1"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
123 {{hi, r7, r7, r3}, true, hi, "hi r7 r7 r3", "hi_r7_r7_r3"},
124 {{vs, r7, r7, r5}, true, vs, "vs r7 r7 r5", "vs_r7_r7_r5"},
125 {{le, r2, r2, r7}, true, le, "le r2 r2 r7", "le_r2_r2_r7"},
128 {{vs, r7, r7, r3}, true, vs, "vs r7 r7 r3", "vs_r7_r7_r3"},
131 {{gt, r7, r7, r7}, true, gt, "gt r7 r7 r7", "gt_r7_r7_r7"},
132 {{ls, r7, r7, r2}, true, ls, "ls r7 r7 r2", "ls_r7_r7_r2"},
135 {{ge, r3, r3, r7}, true, ge, "ge r3 r3 r7", "ge_r3_r3_r7"},
136 {{hi, r5, r5, r7}, true, hi, "hi r5 r5 r7", "hi_r5_r5_r7"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc1889 {{al, r7, r7, 0}, false, al, "al r7 r7 0", "al_r7_r7_0"},
1890 {{al, r7, r7, 1}, false, al, "al r7 r7 1", "al_r7_r7_1"},
1891 {{al, r7, r7, 2}, false, al, "al r7 r7 2", "al_r7_r7_2"},
1892 {{al, r7, r7, 3}, false, al, "al r7 r7 3", "al_r7_r7_3"},
1893 {{al, r7, r7, 4}, false, al, "al r7 r7 4", "al_r7_r7_4"},
1894 {{al, r7, r7, 5}, false, al, "al r7 r7 5", "al_r7_r7_5"},
1895 {{al, r7, r7, 6}, false, al, "al r7 r7 6", "al_r7_r7_6"},
1896 {{al, r7, r7, 7}, false, al, "al r7 r7 7", "al_r7_r7_7"},
1897 {{al, r7, r7, 8}, false, al, "al r7 r7 8", "al_r7_r7_8"},
1898 {{al, r7, r7, 9}, false, al, "al r7 r7 9", "al_r7_r7_9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc102 {{eq, r0, r7}, true, eq, "eq r0 r7", "eq_r0_r7"},
110 {{eq, r1, r7}, true, eq, "eq r1 r7", "eq_r1_r7"},
118 {{eq, r2, r7}, true, eq, "eq r2 r7", "eq_r2_r7"},
126 {{eq, r3, r7}, true, eq, "eq r3 r7", "eq_r3_r7"},
134 {{eq, r4, r7}, true, eq, "eq r4 r7", "eq_r4_r7"},
142 {{eq, r5, r7}, true, eq, "eq r5 r7", "eq_r5_r7"},
150 {{eq, r6, r7}, true, eq, "eq r6 r7", "eq_r6_r7"},
151 {{eq, r7, r0}, true, eq, "eq r7 r0", "eq_r7_r0"},
152 {{eq, r7, r1}, true, eq, "eq r7 r1", "eq_r7_r1"},
153 {{eq, r7, r2}, true, eq, "eq r7 r2", "eq_r7_r2"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc102 {{eq, r0, r7, 0}, true, eq, "eq r0 r7 0", "eq_r0_r7_0"},
110 {{eq, r1, r7, 0}, true, eq, "eq r1 r7 0", "eq_r1_r7_0"},
118 {{eq, r2, r7, 0}, true, eq, "eq r2 r7 0", "eq_r2_r7_0"},
126 {{eq, r3, r7, 0}, true, eq, "eq r3 r7 0", "eq_r3_r7_0"},
134 {{eq, r4, r7, 0}, true, eq, "eq r4 r7 0", "eq_r4_r7_0"},
142 {{eq, r5, r7, 0}, true, eq, "eq r5 r7 0", "eq_r5_r7_0"},
150 {{eq, r6, r7, 0}, true, eq, "eq r6 r7 0", "eq_r6_r7_0"},
151 {{eq, r7, r0, 0}, true, eq, "eq r7 r0 0", "eq_r7_r0_0"},
152 {{eq, r7, r1, 0}, true, eq, "eq r7 r1 0", "eq_r7_r1_0"},
153 {{eq, r7, r2, 0}, true, eq, "eq r7 r2 0", "eq_r7_r2_0"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
104 {{ne, r1, r7, r0}, true, ne, "ne r1 r7 r0", "ne_r1_r7_r0"},
110 {{cs, r1, r4, r7}, true, cs, "cs r1 r4 r7", "cs_r1_r4_r7"},
112 {{ne, r1, r7, r1}, true, ne, "ne r1 r7 r1", "ne_r1_r7_r1"},
116 {{cc, r0, r4, r7}, true, cc, "cc r0 r4 r7", "cc_r0_r4_r7"},
119 {{vs, r4, r5, r7}, true, vs, "vs r4 r5 r7", "vs_r4_r5_r7"},
120 {{cs, r7, r4, r4}, true, cs, "cs r7 r4 r4", "cs_r7_r4_r4"},
122 {{cc, r1, r6, r7}, true, cc, "cc r1 r6 r7", "cc_r1_r6_r7"},
126 {{cs, r7, r2, r5}, true, cs, "cs r7 r2 r5", "cs_r7_r2_r5"},
129 {{ge, r7, r2, r4}, true, ge, "ge r7 r2 r4", "ge_r7_r2_r4"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc153 {{al, r0, r7, 0}, false, al, "al r0 r7 0", "al_r0_r7_0"},
154 {{al, r0, r7, 1}, false, al, "al r0 r7 1", "al_r0_r7_1"},
155 {{al, r0, r7, 2}, false, al, "al r0 r7 2", "al_r0_r7_2"},
156 {{al, r0, r7, 3}, false, al, "al r0 r7 3", "al_r0_r7_3"},
157 {{al, r0, r7, 4}, false, al, "al r0 r7 4", "al_r0_r7_4"},
158 {{al, r0, r7, 5}, false, al, "al r0 r7 5", "al_r0_r7_5"},
159 {{al, r0, r7, 6}, false, al, "al r0 r7 6", "al_r0_r7_6"},
160 {{al, r0, r7, 7}, false, al, "al r0 r7 7", "al_r0_r7_7"},
217 {{al, r1, r7, 0}, false, al, "al r1 r7 0", "al_r1_r7_0"},
218 {{al, r1, r7, 1}, false, al, "al r1 r7 1", "al_r1_r7_1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"},
118 {{ge, r7, r1, 0}, true, ge, "ge r7 r1 0", "ge_r7_r1_0"},
120 {{ge, r1, r7, 0}, true, ge, "ge r1 r7 0", "ge_r1_r7_0"},
123 {{ne, r5, r7, 4}, true, ne, "ne r5 r7 4", "ne_r5_r7_4"},
128 {{ls, r7, r2, 0}, true, ls, "ls r7 r2 0", "ls_r7_r2_0"},
129 {{hi, r4, r7, 6}, true, hi, "hi r4 r7 6", "hi_r4_r7_6"},
136 {{lt, r7, r5, 2}, true, lt, "lt r7 r5 2", "lt_r7_r5_2"},
138 {{ne, r4, r7, 0}, true, ne, "ne r4 r7 0", "ne_r4_r7_0"},
147 {{cs, r7, r0, 4}, true, cs, "cs r7 r0 4", "cs_r7_r0_4"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc97 {{cs, r7, r7, LSL, r2}, true, cs, "cs r7 r7 LSL r2", "cs_r7_r7_LSL_r2"},
106 {{le, r7, r7, LSL, r0}, true, le, "le r7 r7 LSL r0", "le_r7_r7_LSL_r0"},
114 {{pl, r2, r2, ASR, r7}, true, pl, "pl r2 r2 ASR r7", "pl_r2_r2_ASR_r7"},
123 {{cs, r7, r7, ASR, r3}, true, cs, "cs r7 r7 ASR r3", "cs_r7_r7_ASR_r3"},
126 {{ls, r7, r7, LSL, r4}, true, ls, "ls r7 r7 LSL r4", "ls_r7_r7_LSL_r4"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
138 {{vc, r6, r6, ASR, r7}, true, vc, "vc r6 r6 ASR r7", "vc_r6_r6_ASR_r7"},
141 {{cc, r3, r3, LSL, r7}, true, cc, "cc r3 r3 LSL r7", "cc_r3_r3_LSL_r7"},
148 {{ls, r7, r7, LSR, r5}, true, ls, "ls r7 r7 LSR r5", "ls_r7_r7_LSR_r5"},
153 {{mi, r7, r7, LSR, r5}, true, mi, "mi r7 r7 LSR r5", "mi_r7_r7_LSR_r5"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc117 {{hi, r7, r7, 142}, true, hi, "hi r7 r7 142", "hi_r7_r7_142"},
130 {{lt, r7, r7, 224}, true, lt, "lt r7 r7 224", "lt_r7_r7_224"},
136 {{vs, r7, r7, 220}, true, vs, "vs r7 r7 220", "vs_r7_r7_220"},
138 {{cs, r7, r7, 129}, true, cs, "cs r7 r7 129", "cs_r7_r7_129"},
150 {{vs, r7, r7, 194}, true, vs, "vs r7 r7 194", "vs_r7_r7_194"},
152 {{vc, r7, r7, 11}, true, vc, "vc r7 r7 11", "vc_r7_r7_11"},
157 {{ge, r7, r7, 22}, true, ge, "ge r7 r7 22", "ge_r7_r7_22"},
159 {{hi, r7, r7, 195}, true, hi, "hi r7 r7 195", "hi_r7_r7_195"},
175 {{cs, r7, r7, 91}, true, cs, "cs r7 r7 91", "cs_r7_r7_91"},
196 {{vc, r7, r7, 167}, true, vc, "vc r7 r7 167", "vc_r7_r7_167"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc103 {{al, r0, r0, LSL, r7}, false, al, "al r0 r0 LSL r7", "al_r0_r0_LSL_r7"},
111 {{al, r0, r0, LSR, r7}, false, al, "al r0 r0 LSR r7", "al_r0_r0_LSR_r7"},
119 {{al, r0, r0, ASR, r7}, false, al, "al r0 r0 ASR r7", "al_r0_r0_ASR_r7"},
127 {{al, r0, r0, ROR, r7}, false, al, "al r0 r0 ROR r7", "al_r0_r0_ROR_r7"},
135 {{al, r1, r1, LSL, r7}, false, al, "al r1 r1 LSL r7", "al_r1_r1_LSL_r7"},
143 {{al, r1, r1, LSR, r7}, false, al, "al r1 r1 LSR r7", "al_r1_r1_LSR_r7"},
151 {{al, r1, r1, ASR, r7}, false, al, "al r1 r1 ASR r7", "al_r1_r1_ASR_r7"},
159 {{al, r1, r1, ROR, r7}, false, al, "al r1 r1 ROR r7", "al_r1_r1_ROR_r7"},
167 {{al, r2, r2, LSL, r7}, false, al, "al r2 r2 LSL r7", "al_r2_r2_LSL_r7"},
175 {{al, r2, r2, LSR, r7}, false, al, "al r2 r2 LSR r7", "al_r2_r2_LSR_r7"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
99 {{mi, r7, r1, LSR, 10}, true, mi, "mi r7 r1 LSR 10", "mi_r7_r1_LSR_10"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
101 {{eq, r7, r2, ASR, 14}, true, eq, "eq r7 r2 ASR 14", "eq_r7_r2_ASR_14"},
102 {{le, r3, r7, LSR, 2}, true, le, "le r3 r7 LSR 2", "le_r3_r7_LSR_2"},
103 {{mi, r2, r7, LSR, 32}, true, mi, "mi r2 r7 LSR 32", "mi_r2_r7_LSR_32"},
105 {{ne, r3, r7, LSR, 28}, true, ne, "ne r3 r7 LSR 28", "ne_r3_r7_LSR_28"},
109 {{hi, r7, r1, ASR, 30}, true, hi, "hi r7 r1 ASR 30", "hi_r7_r1_ASR_30"},
110 {{mi, r7, r6, ASR, 20}, true, mi, "mi r7 r6 ASR 20", "mi_r7_r6_ASR_20"},
[all …]
Dtest-assembler-cond-rdlow-operand-imm8-t32.cc1888 {{al, r7, 0}, false, al, "al r7 0", "al_r7_0"},
1889 {{al, r7, 1}, false, al, "al r7 1", "al_r7_1"},
1890 {{al, r7, 2}, false, al, "al r7 2", "al_r7_2"},
1891 {{al, r7, 3}, false, al, "al r7 3", "al_r7_3"},
1892 {{al, r7, 4}, false, al, "al r7 4", "al_r7_4"},
1893 {{al, r7, 5}, false, al, "al r7 5", "al_r7_5"},
1894 {{al, r7, 6}, false, al, "al r7 6", "al_r7_6"},
1895 {{al, r7, 7}, false, al, "al r7 7", "al_r7_7"},
1896 {{al, r7, 8}, false, al, "al r7 8", "al_r7_8"},
1897 {{al, r7, 9}, false, al, "al r7 9", "al_r7_9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc108 {{cs, r7, r4, LSL, 28}, true, cs, "cs r7 r4 LSL 28", "cs_r7_r4_LSL_28"},
112 {{hi, r7, r1, LSL, 14}, true, hi, "hi r7 r1 LSL 14", "hi_r7_r1_LSL_14"},
128 {{cc, r0, r7, LSL, 6}, true, cc, "cc r0 r7 LSL 6", "cc_r0_r7_LSL_6"},
130 {{ls, r7, r7, LSL, 11}, true, ls, "ls r7 r7 LSL 11", "ls_r7_r7_LSL_11"},
140 {{cc, r7, r2, LSL, 16}, true, cc, "cc r7 r2 LSL 16", "cc_r7_r2_LSL_16"},
141 {{lt, r7, r3, LSL, 28}, true, lt, "lt r7 r3 LSL 28", "lt_r7_r3_LSL_28"},
151 {{ne, r7, r7, LSL, 26}, true, ne, "ne r7 r7 LSL 26", "ne_r7_r7_LSL_26"},
180 {{vc, r3, r7, LSL, 25}, true, vc, "vc r3 r7 LSL 25", "vc_r3_r7_LSL_25"},
190 {{eq, r7, r1, LSL, 23}, true, eq, "eq r7 r1 LSL 23", "eq_r7_r1_LSL_23"},
197 {{cs, r4, r7, LSL, 15}, true, cs, "cs r4 r7 LSL 15", "cs_r4_r7_LSL_15"},
[all …]
Dtest-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc101 {{ls, r7, 8}, true, ls, "ls r7 8", "ls_r7_8"},
102 {{cs, r7, 201}, true, cs, "cs r7 201", "cs_r7_201"},
109 {{vc, r7, 207}, true, vc, "vc r7 207", "vc_r7_207"},
117 {{lt, r7, 97}, true, lt, "lt r7 97", "lt_r7_97"},
122 {{ne, r7, 171}, true, ne, "ne r7 171", "ne_r7_171"},
143 {{cs, r7, 98}, true, cs, "cs r7 98", "cs_r7_98"},
146 {{gt, r7, 84}, true, gt, "gt r7 84", "gt_r7_84"},
150 {{hi, r7, 32}, true, hi, "hi r7 32", "hi_r7_32"},
151 {{ge, r7, 217}, true, ge, "ge r7 217", "ge_r7_217"},
162 {{cc, r7, 36}, true, cc, "cc r7 36", "cc_r7_36"},
[all …]
Dtest-assembler-rd-rn-rm-t32.cc103 {{r1, r7, r13}, false, al, "r1 r7 r13", "r1_r7_r13"},
113 {{r6, r0, r7}, false, al, "r6 r0 r7", "r6_r0_r7"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
130 {{r6, r5, r7}, false, al, "r6 r5 r7", "r6_r5_r7"},
134 {{r5, r3, r7}, false, al, "r5 r3 r7", "r5_r3_r7"},
137 {{r3, r11, r7}, false, al, "r3 r11 r7", "r3_r11_r7"},
141 {{r8, r7, r14}, false, al, "r8 r7 r14", "r8_r7_r14"},
142 {{r4, r3, r7}, false, al, "r4 r3 r7", "r4_r3_r7"},
146 {{r7, r0, r8}, false, al, "r7 r0 r8", "r7_r0_r8"},
153 {{r7, r8, r2}, false, al, "r7 r8 r2", "r7_r8_r2"},
[all …]
Dtest-assembler-rd-rn-rm-a32.cc103 {{r1, r7, r13}, false, al, "r1 r7 r13", "r1_r7_r13"},
113 {{r6, r0, r7}, false, al, "r6 r0 r7", "r6_r0_r7"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
130 {{r6, r5, r7}, false, al, "r6 r5 r7", "r6_r5_r7"},
134 {{r5, r3, r7}, false, al, "r5 r3 r7", "r5_r3_r7"},
137 {{r3, r11, r7}, false, al, "r3 r11 r7", "r3_r11_r7"},
141 {{r8, r7, r14}, false, al, "r8 r7 r14", "r8_r7_r14"},
142 {{r4, r3, r7}, false, al, "r4 r3 r7", "r4_r3_r7"},
146 {{r7, r0, r8}, false, al, "r7 r0 r8", "r7_r0_r8"},
153 {{r7, r8, r2}, false, al, "r7 r8 r2", "r7_r8_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc136 {{eq, r9, r7, r6, LSL, r1},
156 {{cc, r3, r7, r3, LSL, r13},
176 {{le, r14, r6, r7, ASR, r1},
196 {{eq, r3, r8, r2, LSR, r7},
201 {{mi, r11, r14, r7, LSR, r5},
246 {{ge, r7, r5, r1, LSL, r2},
261 {{hi, r13, r7, r6, ASR, r4},
266 {{hi, r8, r1, r6, LSR, r7},
281 {{ge, r7, r9, r1, ASR, r1},
286 {{vc, r13, r6, r7, LSL, r5},
[all …]
Dtest-assembler-cond-rd-rn-operand-imm12-t32.cc99 {{{al, r12, r7, 1536}, false, al, "al r12 r7 1536", "al_r12_r7_1536"},
100 {{al, r7, r10, 1991}, false, al, "al r7 r10 1991", "al_r7_r10_1991"},
107 {{al, r13, r7, 606}, false, al, "al r13 r7 606", "al_r13_r7_606"},
112 {{al, r13, r7, 3071}, false, al, "al r13 r7 3071", "al_r13_r7_3071"},
113 {{al, r7, r0, 4092}, false, al, "al r7 r0 4092", "al_r7_r0_4092"},
132 {{al, r7, r12, 188}, false, al, "al r7 r12 188", "al_r7_r12_188"},
134 {{al, r13, r7, 98}, false, al, "al r13 r7 98", "al_r13_r7_98"},
142 {{al, r7, r6, 3397}, false, al, "al r7 r6 3397", "al_r7_r6_3397"},
172 {{al, r12, r7, 997}, false, al, "al r12 r7 997", "al_r12_r7_997"},
174 {{al, r7, r12, 2984}, false, al, "al r7 r12 2984", "al_r7_r12_2984"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc98 {{ls, r7, r7, r6}, true, ls, "ls r7 r7 r6", "ls_r7_r7_r6"},
107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"},
109 {{le, r10, r10, r7}, true, le, "le r10 r10 r7", "le_r10_r10_r7"},
110 {{vs, r7, r7, r7}, true, vs, "vs r7 r7 r7", "vs_r7_r7_r7"},
113 {{gt, r7, r7, r12}, true, gt, "gt r7 r7 r12", "gt_r7_r7_r12"},
115 {{ne, r4, r4, r7}, true, ne, "ne r4 r4 r7", "ne_r4_r4_r7"},
127 {{vs, r13, r13, r7}, true, vs, "vs r13 r13 r7", "vs_r13_r13_r7"},
145 {{ne, r7, r7, r5}, true, ne, "ne r7 r7 r5", "ne_r7_r7_r5"},
149 {{mi, r9, r9, r7}, true, mi, "mi r9 r9 r7", "mi_r9_r9_r7"},
151 {{vc, r1, r1, r7}, true, vc, "vc r1 r1 r7", "vc_r1_r1_r7"},
[all …]
Dtest-assembler-cond-rd-operand-rn-t32-in-it-block.cc103 {{eq, r0, r7}, true, eq, "eq r0 r7", "eq_r0_r7"},
118 {{eq, r1, r7}, true, eq, "eq r1 r7", "eq_r1_r7"},
133 {{eq, r2, r7}, true, eq, "eq r2 r7", "eq_r2_r7"},
148 {{eq, r3, r7}, true, eq, "eq r3 r7", "eq_r3_r7"},
163 {{eq, r4, r7}, true, eq, "eq r4 r7", "eq_r4_r7"},
178 {{eq, r5, r7}, true, eq, "eq r5 r7", "eq_r5_r7"},
193 {{eq, r6, r7}, true, eq, "eq r6 r7", "eq_r6_r7"},
201 {{eq, r7, r0}, true, eq, "eq r7 r0", "eq_r7_r0"},
202 {{eq, r7, r1}, true, eq, "eq r7 r1", "eq_r7_r1"},
203 {{eq, r7, r2}, true, eq, "eq r7 r2", "eq_r7_r2"},
[all …]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s21 adc r7, r8, #(0xff << 16)
22 adc r7, r8, #-2147483638
23 adc r7, r8, #42, #2
24 adc r7, r8, #40, #2
25 adc r7, r8, $40, $2
26 adc r7, r8, 40, 2
27 adc r7, r8, (2 * 20), (1 << 1)
37 adcs r7, r8, #40, #2
44 @ CHECK: adc r7, r8, #16711680 @ encoding: [0xff,0x78,0xa8,0xe2]
45 @ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
[all …]
/external/llvm/test/MC/MachO/ARM/
Dcompact-unwind-armv7k.s14 push {r4, r5, r6, r7, lr}
15 add r7, sp, #12
17 .cfi_def_cfa r7, 8
19 .cfi_offset r7, -8
31 push {r4, r5, r7, lr}
32 add r7, sp, #8
33 .cfi_def_cfa r7, 8
35 .cfi_offset r7, -8
49 push {r7, lr}
50 mov r7, sp
[all …]
/external/boringssl/linux-arm/crypto/sha/
Dsha1-armv4-large.S25 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
27 ldmia r0,{r3,r4,r5,r6,r7}
34 mov r7,r7,ror#30 @ [6]
40 add r7,r8,r7,ror#2 @ E+=K_00_19
45 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
49 add r7,r8,r7,ror#2 @ E+=K_00_19
51 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
57 add r7,r7,r9 @ E+=X[i]
60 add r7,r7,r10 @ E+=F_00_19(B,C,D)
70 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-frameaddr.ll9 ; DARWIN-ARM: push {r7}
10 ; DARWIN-ARM: mov r7, sp
11 ; DARWIN-ARM: mov r0, r7
14 ; DARWIN-THUMB2: str r7, [sp, #-4]!
15 ; DARWIN-THUMB2: mov r7, sp
16 ; DARWIN-THUMB2: mov r0, r7
24 ; LINUX-THUMB2: str r7, [sp, #-4]!
25 ; LINUX-THUMB2: mov r7, sp
26 ; LINUX-THUMB2: mov r0, r7
35 ; DARWIN-ARM: push {r7}
[all …]

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