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Searched refs:reg3 (Results 1 – 25 of 52) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
51 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3); in idct32x8_row_even_process_store()
77 reg5 = reg7 + reg3; in idct32x8_row_even_process_store()
78 reg7 = reg7 - reg3; in idct32x8_row_even_process_store()
79 reg3 = vec0; in idct32x8_row_even_process_store()
82 reg2 = reg3 + reg4; in idct32x8_row_even_process_store()
[all …]
Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
49 DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1); in vpx_idct16_1d_rows_msa()
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vpx_idct16_1d_rows_msa()
52 loc1 = reg15 + reg3; in vpx_idct16_1d_rows_msa()
53 reg3 = reg15 - reg3; in vpx_idct16_1d_rows_msa()
85 DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13); in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll39 ; THUMB: movw r[[reg3:[0-9]+]],
40 ; THUMB: movt r[[reg3]],
41 ; THUMB: add r[[reg3]], pc
42 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
44 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
/external/libyuv/files/source/
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
508 reg3 = (v16u8)__msa_pckev_b((v16i8)vec5, (v16i8)vec2); in I422ToRGB24Row_MSA()
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2); in I422ToRGB24Row_MSA()
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
793 reg3 = (v8u16)__msa_ilvev_b(zero, (v16i8)vec3); in ARGBToYRow_MSA()
799 reg3 *= const_0x81; in ARGBToYRow_MSA()
803 reg1 += reg3; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
[all …]
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
[all …]
Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
85 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDown2Box_MSA()
87 reg1 += reg3; in ScaleARGBRowDown2Box_MSA()
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
160 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDownEvenBox_MSA()
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
334 reg3 = __msa_hadd_u_w(vec3, vec3); in ScaleRowDown4Box_MSA()
338 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4); in ScaleRowDown4Box_MSA()
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/external/v8/src/interpreter/
Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
112 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) { in AreContiguous()
115 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
Dbytecode-register.h66 Register reg3 = Register(),
/external/llvm/test/CodeGen/AMDGPU/
Dpv-packing.ll6 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
14 %6 = extractelement <4 x float> %reg3, i32 0
15 %7 = extractelement <4 x float> %reg3, i32 1
16 %8 = extractelement <4 x float> %reg3, i32 2
Dload-input-fold.ll3 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
13 %8 = extractelement <4 x float> %reg3, i32 0
14 %9 = extractelement <4 x float> %reg3, i32 1
15 %10 = extractelement <4 x float> %reg3, i32 2
16 %11 = extractelement <4 x float> %reg3, i32 3
Dpv.ll6 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
16 %8 = extractelement <4 x float> %reg3, i32 0
17 %9 = extractelement <4 x float> %reg3, i32 1
18 %10 = extractelement <4 x float> %reg3, i32 2
19 %11 = extractelement <4 x float> %reg3, i32 3
/external/valgrind/none/tests/s390x/
Dcksm.c27 register uint64_t reg3 asm("3") = len; in cksm_by_insn()
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); in cksm_by_insn()
36 len = reg3; in cksm_by_insn()
/external/elfutils/tests/
Drun-varlocs.sh68 [40051c,40052a) {reg3}
107 [400408,400421) {reg3}
Drun-addrcfi.sh36 integer reg3 (%ebx): same_value
83 integer reg3 (%ebx): same_value
135 integer reg3 (%rbx): undefined
201 integer reg3 (%rbx): undefined
305 integer reg3 (r3): undefined
1327 integer reg3 (r3): undefined
2355 integer reg3 (r3): undefined
3381 integer reg3 (%r3): undefined
3458 integer reg3 (%r3): undefined
3536 integer reg3 (r3): undefined
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/external/vixl/src/aarch64/
Doperands-aarch64.h476 const CPURegister& reg3 = NoReg,
490 const CPURegister& reg3 = NoCPUReg,
503 const VRegister& reg3 = NoVReg,
513 const VRegister& reg3 = NoVReg,
522 CPURegister reg3 = NoCPUReg,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dmacro-assembler-aarch64.cc2723 const Register& reg3, in Include() argument
2727 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Include()
2737 const FPRegister& reg3, in Include() argument
2740 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Include()
2757 const Register& reg3, in Exclude() argument
2760 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Exclude()
2767 const FPRegister& reg3, in Exclude() argument
2770 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Exclude()
2777 const CPURegister& reg3, in Exclude() argument
2782 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Exclude()
Dassembler-aarch64.cc4750 const CPURegister& reg3, in AreAliased() argument
4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
4789 const CPURegister& reg3, in AreSameSizeAndType() argument
4798 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
4810 const VRegister& reg3, in AreSameFormat() argument
4815 match &= !reg3.IsValid() || reg3.IsSameFormat(reg1); in AreSameFormat()
4823 const VRegister& reg3, in AreConsecutive() argument
4833 if (!reg3.IsValid()) { in AreConsecutive()
4835 } else if (reg3.GetCode() != ((reg2.GetCode() + 1) % kNumberOfVRegisters)) { in AreConsecutive()
4841 } else if (reg4.GetCode() != ((reg3.GetCode() + 1) % kNumberOfVRegisters)) { in AreConsecutive()
/external/vixl/src/aarch32/
Dinstructions-aarch32.h463 RegisterList(Register reg1, Register reg2, Register reg3)
465 RegisterToList(reg3)) {}
466 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
468 RegisterToList(reg3) | RegisterToList(reg4)) {}
552 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList() argument
554 RegisterToList(reg3)) {} in VRegisterList()
555 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList() argument
557 RegisterToList(reg3) | RegisterToList(reg4)) {} in VRegisterList()
Dmacro-assembler-aarch32.cc745 CPURegister reg3, in Printf() argument
755 PushRegister(reg3); in Printf()
762 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) | in Printf()
767 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() + in Printf()
788 if (reg3.GetType() == CPURegister::kRRegister) { in Printf()
789 available_registers.Remove(Register(reg3.GetCode())); in Printf()
803 PushRegister(reg3); in Printf()
814 PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type); in Printf()
/external/llvm/lib/Target/X86/
DX86InstrFMA.td137 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
139 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;
/external/v8/src/arm64/
Dassembler-arm64.h348 Register reg3 = NoReg,
356 const CPURegister& reg3 = NoReg,
369 const CPURegister& reg3 = NoCPUReg,
388 CPURegister reg3 = NoCPUReg,
390 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
392 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-arm64.cc208 Register reg3, Register reg4) { in GetAllocatableRegisterThatIsNotOneOf() argument
209 CPURegList regs(reg1, reg2, reg3, reg4); in GetAllocatableRegisterThatIsNotOneOf()
223 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
232 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
260 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
266 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/v8/src/full-codegen/
Dfull-codegen.h373 void PushOperands(Register reg1, Register reg2, Register reg3);
374 void PushOperands(Register reg1, Register reg2, Register reg3, Register reg4);
/external/v8/src/arm/
Dmacro-assembler-arm.cc3841 Register reg3, in GetRegisterThatIsNotOneOf() argument
3848 if (reg3.is_valid()) regs |= reg3.bit(); in GetRegisterThatIsNotOneOf()
3906 Register reg3, in AreAliased() argument
3913 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
3919 if (reg3.is_valid()) regs |= reg3.bit(); in AreAliased()
/external/llvm/include/llvm/Support/
DDwarf.def204 HANDLE_DW_OP(0x53, reg3)

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