/external/llvm/test/CodeGen/Mips/ |
D | rotate.ll | 8 ; CHECK: rotrv $2, $4 12 ; MM32: rotrv $2, $4, $2 33 ; CHECK: rotrv $2, $4, $5 35 ; MM32: rotrv $2, $4, $5
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/external/llvm/test/MC/Mips/ |
D | rotations32.s | 15 # CHECK-32R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46] 22 # CHECK-32R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46] 55 # CHECK-32R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46] 61 # CHECK-32R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
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D | micromips-shift-instructions.s | 17 # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48] 37 # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] 54 rotrv $9, $6, $7
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D | rotations64.s | 15 # CHECK-64R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46] 22 # CHECK-64R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46] 55 # CHECK-64R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46] 61 # CHECK-64R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
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D | mips64-alu-instructions.s | 18 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] 46 rotrv $9, $6, $7
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D | mips-alu-instructions.s | 20 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] 51 rotrv $9, $6, $7
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/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
D | rotate.ll | 3 ; CHECK: rotrv $2, $4 22 ; CHECK: rotrv $2, $4, $5
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/external/valgrind/none/tests/mips32/ |
D | MIPS32int.stdout.exp-mips32r2-LE | 1048 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff 1049 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00 1050 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff 1051 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 1052 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001 1053 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 1054 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff 1055 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 1056 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000 1057 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 [all …]
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D | MIPS32int.stdout.exp-mips32r2-BE | 1048 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff 1049 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00 1050 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff 1051 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 1052 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001 1053 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 1054 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff 1055 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 1056 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000 1057 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 [all …]
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/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 28 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 36 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips32/ |
D | invalid-mips32r2.s | 30 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/mips32r3/ |
D | valid.s | 168 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/llvm/test/MC/Mips/mips32r5/ |
D | valid.s | 169 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 168 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/llvm/test/MC/Mips/mips64r3/ |
D | valid.s | 235 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/llvm/test/MC/Mips/mips64r2/ |
D | valid.s | 235 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/llvm/test/MC/Mips/mips64r5/ |
D | valid.s | 236 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
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/external/valgrind/none/tests/mips64/ |
D | shift_instructions.stdout.exp-mips64r2 | 19457 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4 19458 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03 19459 rotrv $t0, $t1, $t2 :: rd 0x608edb82, rs 0x9823b6e, rt 0xffffffffb8757bda 19460 rotrv $t0, $t1, $t2 :: rd 0x36c86a19, rs 0xd4326d9, rt 0xffffffffbcb4666d 19461 rotrv $t0, $t1, $t2 :: rd 0xffffffffdc130476, rs 0x130476dc, rt 0xffffffffa2f33668 19462 rotrv $t0, $t1, $t2 :: rd 0x2f8ad6d6, rs 0x17c56b6b, rt 0xffffffffa6322bdf 19463 rotrv $t0, $t1, $t2 :: rd 0xffffffffc86a1936, rs 0x1a864db2, rt 0xffffffffab710d06 19464 rotrv $t0, $t1, $t2 :: rd 0xffffffffa8028f23, rs 0x1e475005, rt 0xffffffffafb010b1 19465 rotrv $t0, $t1, $t2 :: rd 0xffffffffdb82608e, rs 0x2608edb8, rt 0xffffffff97ffad0c 19466 rotrv $t0, $t1, $t2 :: rd 0x593e01e4, rs 0x22c9f00f, rt 0xffffffff933eb0bb [all …]
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/external/llvm/test/MC/Mips/mips2/ |
D | invalid-mips32r2.s | 62 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm/test/MC/Mips/micromips64r6/ |
D | valid.s | 48 …rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x…
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/external/llvm/test/MC/Mips/micromips/ |
D | invalid.s | 46 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/llvm/test/MC/Mips/micromips32r6/ |
D | valid.s | 87 …rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x…
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/external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
D | valid.txt | 89 0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
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D | valid-el.txt | 89 0xc7 0x00 0xd0 0x48 # CHECK: rotrv $9, $6, $7
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