| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 299 rshrn2 v0.16b, v1.8h, #3
300 rshrn2 v0.8h, v1.4s, #3
301 rshrn2 v0.4s, v1.2d, #3
|
| D | arm64-advsimd.s | 1458 rshrn2.16b v0, v0, #2
1460 rshrn2.8h v0, v0, #4
1462 rshrn2.4s v0, v0, #6
1630 ; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
1632 ; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
1634 ; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
1799 rshrn2 v8.16b, v9.8h, #2
1801 rshrn2 v6.8h, v7.4s, #4
1803 rshrn2 v4.4s, v5.2d, #6
1870 ; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
[all …]
|
| D | neon-diagnostics.s | 1868 rshrn2 v0.16b, v1.8h, #17
1869 rshrn2 v0.8h, v1.4s, #33
1870 rshrn2 v0.4s, v1.2d, #65
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_arm64_neon.S | 532 …rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13…
533 …rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12…
534 …rshrn2 v4.8h, v24.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11…
535 …rshrn2 v5.8h, v20.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10…
616 …rshrn2 v6.8h, v17.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13…
617 …rshrn2 v7.8h, v29.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12…
618 …rshrn2 v8.8h, v25.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11…
619 …rshrn2 v9.8h, v21.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10…
730 …rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13…
731 …rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12…
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-shift.ll | 368 ; CHECK: rshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
379 ; CHECK: rshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
390 ; CHECK: rshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
|
| D | arm64-vecFold.ll | 98 ; CHECK-NEXT: rshrn2.16b v0, v2, #6
|
| D | arm64-vshift.ll | 645 ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
655 ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
665 ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 2600 LogicVRegister Simulator::rshrn2(VectorFormat vform, in rshrn2() function in vixl::aarch64::Simulator
2743 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
3404 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn2()
3448 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn2()
|
| D | simulator-aarch64.h | 2598 LogicVRegister rshrn2(VectorFormat vform,
|
| D | assembler-aarch64.h | 2280 void rshrn2(const VRegister& vd, const VRegister& vn, int shift);
|
| D | macro-assembler-aarch64.h | 2405 V(rshrn2, Rshrn2) \
|
| D | simulator-aarch64.cc | 5069 rshrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
|
| D | assembler-aarch64.cc | 3773 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) { in rshrn2() function in vixl::aarch64::Assembler
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 989 # CHECK: rshrn2 v0.16b, v1.8h, #3
990 # CHECK: rshrn2 v0.8h, v1.4s, #3
991 # CHECK: rshrn2 v0.4s, v1.2d, #3
|
| D | arm64-advsimd.txt | 2033 # CHECK: rshrn2.16b v0, v0, #0x6
2035 # CHECK: rshrn2.8h v0, v0, #0xc
2037 # CHECK: rshrn2.4s v0, v0, #0x1a
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1107 0x~~~~~~~~~~~~~~~~ 4f088cc3 rshrn2 v3.16b, v6.8h, #8
1108 0x~~~~~~~~~~~~~~~~ 4f278fa0 rshrn2 v0.4s, v29.2d, #25
1109 0x~~~~~~~~~~~~~~~~ 4f118f5b rshrn2 v27.8h, v26.4s, #15
|
| D | log-disasm | 1107 0x~~~~~~~~~~~~~~~~ 4f088cc3 rshrn2 v3.16b, v6.8h, #8
1108 0x~~~~~~~~~~~~~~~~ 4f278fa0 rshrn2 v0.4s, v29.2d, #25
1109 0x~~~~~~~~~~~~~~~~ 4f118f5b rshrn2 v27.8h, v26.4s, #15
|
| D | log-all | 3037 0x~~~~~~~~~~~~~~~~ 4f088cc3 rshrn2 v3.16b, v6.8h, #8
3039 0x~~~~~~~~~~~~~~~~ 4f278fa0 rshrn2 v0.4s, v29.2d, #25
3041 0x~~~~~~~~~~~~~~~~ 4f118f5b rshrn2 v27.8h, v26.4s, #15
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1341 __ rshrn2(v3.V16B(), v6.V8H(), 8); in GenerateTestSequenceNEON() local
1342 __ rshrn2(v0.V4S(), v29.V2D(), 25); in GenerateTestSequenceNEON() local
1343 __ rshrn2(v27.V8H(), v26.V4S(), 15); in GenerateTestSequenceNEON() local
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27491 rshrn2 v4.4s, v29.2d, #1 37504bd226ef2969239d20cb79b6e4f5 f7238a1daeeb282ed57ffecc46f208d7 d77…
27492 rshrn2 v4.4s, v29.2d, #32 1cc748e69a8e12192d1a490727a15463 9e032ba23f489352e512e49492f3f1a0 9e…
27495 rshrn2 v4.8h, v29.4s, #1 e93c190f33ee4cd836fc9169e3db77ed 1e1a025533fef6d8b0f5867e546ecd9a 012…
27496 rshrn2 v4.8h, v29.4s, #16 a394a6478ef9bcb2306bb10b7103fed1 c690e3c3cf33280015d4ef00cf02bbe5 c6…
27499 rshrn2 v4.16b, v29.8h, #1 f6a7496b02d2e287f95f0247b34ee01d 73ce92d7945ca60fafe62b266960e4b6 e76…
27500 rshrn2 v4.16b, v29.8h, #8 5ef2688a3398cbd170d20361e6423001 2817650c662db286f1a8d6ffe99ffce0 286…
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2919 void rshrn2(const VRegister& vd,
|