| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsub.ll | 66 ;CHECK: rsubhn.8b
69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
75 ;CHECK: rsubhn.4h
78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
84 ;CHECK: rsubhn.2s
87 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
93 ;CHECK: rsubhn.8b
95 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwi…
96 …%vrsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) n…
103 ;CHECK: rsubhn.4h
[all …]
|
| D | arm64-vecFold.ll | 111 ; CHECK: rsubhn.8b v0, v0, v1
114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun…
115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no…
144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
|
| D | arm64-neon-3vdiff.ll | 41 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>)
43 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>)
45 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>)
955 ; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
957 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
963 ; CHECK: rsubhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
965 %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
971 ; CHECK: rsubhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
973 %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
979 ; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 401 rsubhn v0.8b, v1.8h, v2.8h
402 rsubhn v0.4h, v1.4s, v2.4s
403 rsubhn v0.2s, v1.2d, v2.2d
|
| D | neon-diagnostics.s | 2819 rsubhn v0.8b, v1.8h, v2.8b
2820 rsubhn v0.4h, v1.4s, v2.4h
2821 rsubhn v0.2s, v1.2d, v2.2s
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1458 # CHECK: rsubhn v0.8b, v1.8h, v2.8h
1459 # CHECK: rsubhn v0.4h, v1.4s, v2.4s
1460 # CHECK: rsubhn v0.2s, v1.2d, v2.2d
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 2734 GEN_BINARY_TEST(rsubhn, 2s, 2d, 2d)
2736 GEN_BINARY_TEST(rsubhn, 4h, 4s, 4s)
2738 GEN_BINARY_TEST(rsubhn, 8b, 8h, 8h)
|
| D | fp_and_simd.stdout.exp | 26965 rsubhn v9.2s, v7.2d, v8.2d 05349f4ad2ee4133e08c964a68b6e61b d104a604b0404d63161107838b952a99 000…
26967 rsubhn v9.4h, v7.4s, v8.4s 50ee42785838efb6f9983ba9b3a2dbfd 32e86dc600fde27927fcc446d6ce3061 000…
26969 rsubhn v9.8b, v7.8h, v8.8h 79526b3762c87e9a13f68777f17941ba b3cdbec4fee108e3cc21fd348f622409 000…
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1110 0x~~~~~~~~~~~~~~~~ 2ea4632f rsubhn v15.2s, v25.2d, v4.2d
1111 0x~~~~~~~~~~~~~~~~ 2e636137 rsubhn v23.4h, v9.4s, v3.4s
1112 0x~~~~~~~~~~~~~~~~ 2e3863c6 rsubhn v6.8b, v30.8h, v24.8h
|
| D | log-disasm | 1110 0x~~~~~~~~~~~~~~~~ 2ea4632f rsubhn v15.2s, v25.2d, v4.2d
1111 0x~~~~~~~~~~~~~~~~ 2e636137 rsubhn v23.4h, v9.4s, v3.4s
1112 0x~~~~~~~~~~~~~~~~ 2e3863c6 rsubhn v6.8b, v30.8h, v24.8h
|
| D | log-all | 3043 0x~~~~~~~~~~~~~~~~ 2ea4632f rsubhn v15.2s, v25.2d, v4.2d
3045 0x~~~~~~~~~~~~~~~~ 2e636137 rsubhn v23.4h, v9.4s, v3.4s
3047 0x~~~~~~~~~~~~~~~~ 2e3863c6 rsubhn v6.8b, v30.8h, v24.8h
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1344 __ rsubhn(v15.V2S(), v25.V2D(), v4.V2D()); in GenerateTestSequenceNEON() local
1345 __ rsubhn(v23.V4H(), v9.V4S(), v3.V4S()); in GenerateTestSequenceNEON() local
1346 __ rsubhn(v6.V8B(), v30.V8H(), v24.V8H()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4209 DEFINE_TEST_NEON_3DIFF_NARROW(rsubhn, Basic)
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2666 V(rsubhn) \
|
| D | assembler-aarch64.h | 2451 void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | macro-assembler-aarch64.h | 2165 V(rsubhn, Rsubhn) \
|
| D | simulator-aarch64.cc | 3670 rsubhn(vf, rd, rn, rm); in VisitNEON3Different()
|
| D | logic-aarch64.cc | 3431 LogicVRegister Simulator::rsubhn(VectorFormat vform, in rsubhn() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 1954 V(rsubhn, NEON_RSUBHN, vd.IsD()) \
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2928 void rsubhn(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3536 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
|