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Searched refs:saddl (Results 1 – 25 of 27) sorted by relevance

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/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s337 saddl v26.4s, v31.4h, v20.4h //// a0 + a5 (set1)
349 saddl v20.4s, v31.4h, v21.4h //// a0 + a5 (set2)
366 saddl v2.4s, v31.4h, v22.4h //// a0 + a5 (set3)
379 saddl v26.4s, v31.4h, v23.4h //// a0 + a5 (set4)
388 saddl v22.4s, v31.4h, v24.4h //// a0 + a5 (set5)
453 saddl v26.4s, v31.4h, v20.4h //// a0 + a5 (set1)
465 saddl v20.4s, v31.4h, v21.4h //// a0 + a5 (set2)
482 saddl v6.4s, v31.4h, v22.4h //// a0 + a5 (set3)
495 saddl v26.4s, v31.4h, v23.4h //// a0 + a5 (set4)
504 saddl v22.4s, v31.4h, v24.4h //// a0 + a5 (set5)
[all …]
/external/libavc/common/armv8/
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s139 saddl v26.4s, v18.4h, v23.4h
164 saddl v26.4s, v0.4h, v20.4h
220 saddl v26.4s, v18.4h, v23.4h
246 saddl v26.4s, v2.4h, v20.4h
299 saddl v26.4s, v18.4h, v23.4h
325 saddl v26.4s, v4.4h, v20.4h
381 saddl v26.4s, v18.4h, v23.4h
406 saddl v26.4s, v6.4h, v20.4h
483 saddl v30.4s, v12.4h, v22.4h
514 saddl v30.4s, v28.4h, v22.4h
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s202 saddl v26.4s, v18.4h, v22.4h
227 saddl v26.4s, v0.4h, v20.4h
289 saddl v26.4s, v18.4h, v22.4h
315 saddl v26.4s, v2.4h, v20.4h
373 saddl v26.4s, v18.4h, v22.4h
399 saddl v26.4s, v4.4h, v20.4h
460 saddl v26.4s, v18.4h, v22.4h
485 saddl v26.4s, v6.4h, v20.4h
568 saddl v30.4s, v12.4h, v22.4h
599 saddl v30.4s, v28.4h, v22.4h
[all …]
Dih264_ihadamard_scaling_av8.s109 saddl v4.4s, v0.4h, v3.4h //x0 = x4 + x7
110 saddl v5.4s, v1.4h, v2.4h //x1 = x5 + x6
224 saddl v2.4s, v0.4h, v1.4h //i4_x0 = i4_x4 + i4_x5;...x2
Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s258 saddl v18.4s, v6.4h, v16.4h
294 saddl v18.4s, v8.4h, v20.4h
338 saddl v18.4s, v10.4h, v8.4h
364 saddl v18.4s, v12.4h, v28.4h
507 saddl v18.4s, v6.4h, v16.4h
541 saddl v18.4s, v8.4h, v20.4h
583 saddl v18.4s, v10.4h, v8.4h
609 saddl v18.4s, v12.4h, v28.4h
751 saddl v18.4s, v6.4h, v16.4h
787 saddl v18.4s, v8.4h, v20.4h
[all …]
Dih264_resi_trans_quant_av8.s485 saddl v4.4s, v0.4h, v3.4h //x0 = x4 + x7;
486 saddl v5.4s, v1.4h, v2.4h //x1 = x5 + x6;
634 saddl v2.4s, v0.4h, v1.4h //x0 = x4 + x5;, x2 = x6 + x7;
Dih264_iquant_itrans_recon_av8.s664 saddl v24.4s, v13.4h, v11.4h
670 saddl v28.4s, v15.4h, v9.4h
/external/libhevc/common/arm64/
Dihevc_itrans_recon_4x4.s149 saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
183 saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s17 saddl v0.8h, v1.8b, v2.8b
18 saddl v0.4s, v1.4h, v2.4h
19 saddl v0.2d, v1.2s, v2.2s
Dneon-diagnostics.s2099 saddl v0.8h, v1.8h, v2.8b
2100 saddl v0.4s, v1.4s, v2.4h
2101 saddl v0.2d, v1.2d, v2.2s
/external/llvm/test/CodeGen/AArch64/
Darm64-vadd.ll128 ;CHECK: saddl.8h
139 ;CHECK: saddl.4s
150 ;CHECK: saddl.2d
Darm64-neon-3vdiff.ll55 ; CHECK: saddl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
65 ; CHECK: saddl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
75 ; CHECK: saddl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1125 # CHECK: saddl v0.8h, v1.8b, v2.8b
1126 # CHECK: saddl v0.4s, v1.4h, v2.4h
1127 # CHECK: saddl v0.2d, v1.2s, v2.2s
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1146 0x~~~~~~~~~~~~~~~~ 0eae0145 saddl v5.2d, v10.2s, v14.2s
1147 0x~~~~~~~~~~~~~~~~ 0e6f0072 saddl v18.4s, v3.4h, v15.4h
1148 0x~~~~~~~~~~~~~~~~ 0e37004f saddl v15.8h, v2.8b, v23.8b
Dlog-disasm1146 0x~~~~~~~~~~~~~~~~ 0eae0145 saddl v5.2d, v10.2s, v14.2s
1147 0x~~~~~~~~~~~~~~~~ 0e6f0072 saddl v18.4s, v3.4h, v15.4h
1148 0x~~~~~~~~~~~~~~~~ 0e37004f saddl v15.8h, v2.8b, v23.8b
Dlog-all3115 0x~~~~~~~~~~~~~~~~ 0eae0145 saddl v5.2d, v10.2s, v14.2s
3117 0x~~~~~~~~~~~~~~~~ 0e6f0072 saddl v18.4s, v3.4h, v15.4h
3119 0x~~~~~~~~~~~~~~~~ 0e37004f saddl v15.8h, v2.8b, v23.8b
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1380 __ saddl(v5.V2D(), v10.V2S(), v14.V2S()); in GenerateTestSequenceNEON() local
1381 __ saddl(v18.V4S(), v3.V4H(), v15.V4H()); in GenerateTestSequenceNEON() local
1382 __ saddl(v15.V8H(), v2.V8B(), v23.V8B()); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4188 DEFINE_TEST_NEON_3DIFF_LONG(saddl, Basic)
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2356 LogicVRegister saddl(VectorFormat vform,
Dassembler-aarch64.h2175 void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
Dmacro-assembler-aarch64.h2173 V(saddl, Saddl) \
Dsimulator-aarch64.cc3532 saddl(vf_l, rd, rn, rm); in VisitNEON3Different()
Dlogic-aarch64.cc2889 LogicVRegister Simulator::saddl(VectorFormat vform, in saddl() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc1899 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3008 void saddl(const VRegister& vd,

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