| /external/libavc/common/armv8/ |
| D | ih264_weighted_pred_av8.s | 154 saddw v4.8h, v4.8h , v3.8b //adding offset for rows 1,2
155 saddw v6.8h, v6.8h , v3.8b //adding offset for rows 3,4
188 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1
190 saddw v6.8h, v6.8h , v3.8b //adding offset for row 2
192 saddw v8.8h, v8.8h , v3.8b //adding offset for row 3
194 saddw v10.8h, v10.8h , v3.8b //adding offset for row 4
234 saddw v12.8h, v12.8h , v3.8b //adding offset for row 1L
236 saddw v14.8h, v14.8h , v3.8b //adding offset for row 1H
239 saddw v16.8h, v16.8h , v3.8b //adding offset for row 2L
242 saddw v18.8h, v18.8h , v3.8b //adding offset for row 2H
[all …]
|
| D | ih264_weighted_bi_pred_av8.s | 185 saddw v4.8h, v4.8h , v3.8b //adding offset for rows 1,2
186 saddw v8.8h, v8.8h , v3.8b //adding offset for rows 3,4
225 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1
227 saddw v8.8h, v8.8h , v3.8b //adding offset for row 2
228 saddw v12.8h, v12.8h , v3.8b //adding offset for row 3
230 saddw v16.8h, v16.8h , v3.8b //adding offset for row 4
287 saddw v20.8h, v20.8h , v3.8b //adding offset for row 1L
289 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1H
291 saddw v24.8h, v24.8h , v3.8b //adding offset for row 2L
293 saddw v8.8h, v8.8h , v3.8b //adding offset for row 2H
[all …]
|
| D | ih264_iquant_itrans_recon_av8.s | 677 saddw v24.4s, v24.4s, v9.4h
680 saddw v26.4s, v26.4s, v13.4h
690 saddw v24.4s, v24.4s, v16.4h
693 saddw v26.4s, v26.4s, v19.4h
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 301 saddw v0.8h, v1.8h, v2.8b
302 saddw v0.4s, v1.4s, v2.4h
303 saddw v0.2d, v1.2d, v2.2s
|
| D | neon-diagnostics.s | 2647 saddw v0.8h, v1.8h, v2.8h
2648 saddw v0.4s, v1.4s, v2.4s
2649 saddw v0.2d, v1.2d, v2.2d
|
| /external/libhevc/common/arm64/ |
| D | ihevc_deblk_luma_horz.s | 505 saddw v4.8h, v6.8h , v7.8b
530 saddw v14.8h, v14.8h , v7.8b
537 saddw v16.8h, v16.8h , v14.8b
569 saddw v16.8h, v16.8h , v14.8b
|
| D | ihevc_deblk_luma_vert.s | 530 saddw v16.8h, v16.8h , v20.8b
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vadd.ll | 360 ;CHECK: saddw.8h
370 ;CHECK: saddw.4s
380 ;CHECK: saddw.2d
|
| D | arm64-neon-3vdiff.ll | 187 ; CHECK: saddw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
196 ; CHECK: saddw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
205 ; CHECK: saddw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1370 # CHECK: saddw v0.8h, v1.8h, v2.8b
1371 # CHECK: saddw v0.4s, v1.4s, v2.4h
1372 # CHECK: saddw v0.2d, v1.2d, v2.2s
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1163 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s
1164 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h
1165 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b
|
| D | log-disasm | 1163 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s
1164 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h
1165 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b
|
| D | log-all | 3149 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s
3151 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h
3153 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1397 __ saddw(v24.V2D(), v11.V2D(), v18.V2S()); in GenerateTestSequenceNEON() local
1398 __ saddw(v13.V4S(), v12.V4S(), v6.V4H()); in GenerateTestSequenceNEON() local
1399 __ saddw(v19.V8H(), v19.V8H(), v7.V8B()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4189 DEFINE_TEST_NEON_3DIFF_WIDE(saddw, Basic)
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2364 LogicVRegister saddw(VectorFormat vform,
|
| D | assembler-aarch64.h | 2181 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | macro-assembler-aarch64.h | 2175 V(saddw, Saddw) \
|
| D | simulator-aarch64.cc | 3634 saddw(vf_l, rd, rn, rm); in VisitNEON3Different()
|
| D | logic-aarch64.cc | 2913 LogicVRegister Simulator::saddw(VectorFormat vform, in saddw() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 1984 void Assembler::saddw(const VRegister& vd, in saddw() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3042 void saddw(const VRegister& vd,
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27423 saddw v5.8h, v13.8h, v31.8b 150441fc290cecd7a0d44738f93a19fe c0ffdfe5519ab73c571f8ec9e0287451 …
27425 saddw v5.4s, v13.4s, v31.4h c1ca0c654122f2928433d66203fc0810 61228e21dffadc7e6f2c05343a0fc203 …
27427 saddw v5.2d, v13.2d, v31.2s 5da7550bfd8e4e31b1d6dc76db03f55b 0c30c09574495bcc9f43c7baa0fe6563 …
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3544 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
|