| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 245 MI->getOperand(0).setReg(KilledProdReg); in processBlock()
246 MI->getOperand(1).setReg(KilledProdReg); in processBlock()
247 MI->getOperand(3).setReg(AddendSrcReg); in processBlock()
264 MI->getOperand(2).setReg(AddendSrcReg); in processBlock()
269 MI->getOperand(2).setReg(OtherProdReg); in processBlock()
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| D | PPCMIPeephole.cpp | 156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
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| D | PPCVSXCopy.cpp | 125 SrcMO.setReg(NewVReg); in processBlock()
147 SrcMO.setReg(NewVReg); in processBlock()
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| D | PPCQPXLoadSplat.cpp | 114 MI->getOperand(0).setReg(SplatSubReg); in runOnMachineFunction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
360 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
372 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
503 MO.setReg(High); in HexagonProcessInstruction()
515 MO.setReg(High); in HexagonProcessInstruction()
528 MO.setReg(High); in HexagonProcessInstruction()
561 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
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| D | HexagonPeephole.cpp | 252 MI.getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
282 MI.getOperand(PR).setReg(POrig); in runOnMachineFunction()
305 Dst.setReg(Src.getReg()); in ChangeOpInto()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 110 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
111 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
112 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
150 MO.setReg(Pred[j].getReg()); in PredicateInstruction()
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| D | AntiDepBreaker.h | 65 MI->getOperand(0).setReg(NewReg); in UpdateDbgValue()
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| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
473 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
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| D | SparcRegisterInfo.cpp | 190 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
203 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | FPMover.cpp | 115 MI->getOperand(0).setReg(EvenDestReg); in runOnMachineBasicBlock()
116 MI->getOperand(1).setReg(EvenSrcReg); in runOnMachineBasicBlock()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1604 MO.setReg(matchRegister(Reg1)); in processInstruction()
1619 MO.setReg(matchRegister(Reg1)); in processInstruction()
1635 MO.setReg(matchRegister(Reg1)); in processInstruction()
1651 MO.setReg(MatchRegisterName(R1)); in processInstruction()
1975 Rss.setReg(matchRegister(Reg1)); in processInstruction()
2002 Rs.setReg(matchRegister(RegPair)); in processInstruction()
2008 Rs.setReg(matchRegister(RegPair)); in processInstruction()
2021 Rs.setReg(matchRegister(RegPair)); in processInstruction()
2027 Rs.setReg(matchRegister(RegPair)); in processInstruction()
2040 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyPeephole.cpp | 65 MO.setReg(NewReg); in MaybeRewriteToDrop()
94 MO.setReg(NewReg); in MaybeRewriteToFallthrough()
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| D | WebAssemblyRegStackify.cpp | 453 Def->getOperand(0).setReg(NewReg); in MoveForSingleUse()
454 Op.setReg(NewReg); in MoveForSingleUse()
486 Op.setReg(NewReg); in RematerializeCheapDef()
555 Op.setReg(TeeReg); in MoveAndTeeForMultiUse()
556 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse()
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| D | WebAssemblyReplacePhysRegs.cpp | 90 MO.setReg(VReg); in runOnMachineFunction()
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| /external/llvm/lib/CodeGen/ |
| D | AntiDepBreaker.h | 61 MI.getOperand(0).setReg(NewReg); in UpdateDbgValue()
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| D | TailDuplicator.cpp | 352 MO.setReg(NewReg); in duplicateInstruction()
383 MO.setReg(VI->second.Reg); in duplicateInstruction()
401 MO.setReg(NewReg); in duplicateInstruction()
477 II->getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
489 II->getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 427 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
462 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 214 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg()); in foldVGPRCopyIntoRegSequence()
232 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
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| D | R600EmitClauseMarkers.cpp | 167 Consts[i].first->setReg( in SubstituteKCacheBank()
171 Consts[i].first->setReg( in SubstituteKCacheBank()
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| D | R600InstrInfo.cpp | 967 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
970 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
1001 .setReg(Pred[2].getReg()); in PredicateInstruction()
1003 .setReg(Pred[2].getReg()); in PredicateInstruction()
1005 .setReg(Pred[2].getReg()); in PredicateInstruction()
1007 .setReg(Pred[2].getReg()); in PredicateInstruction()
1015 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1375 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()
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| D | R600ExpandSpecialInstrs.cpp | 88 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
94 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsOptimizePICCall.cpp | 138 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 96 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
101 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64DeadRegisterDefinitionsPass.cpp | 134 MO.setReg(NewReg); in processMachineBasicBlock()
|