/external/llvm/test/CodeGen/X86/ |
D | dagcombine-and-setcc.ll | 10 ; (and (setgt X, true), (setgt Y, true)) -> (setgt (or X, Y), true)
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/external/clang/test/CodeGen/ |
D | BasicInstrs.c | 23 _Bool setgt(int X, int Y) { in setgt() function
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonSelectCCInfo.td | 100 // setgt-64. 111 // setlt-64 -> setgt-64.
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D | HexagonInstrInfoV3.td | 146 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>; 174 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
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D | HexagonInstrInfoVector.td | 228 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>; 232 def: vcmp_vi1_pat<A2_vcmphgt, setgt, V4I16, v4i1>; 286 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)), 293 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
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D | HexagonInstrInfo.td | 101 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>; 287 // since seteq/setgt/etc. are defined as ParFrags. 293 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>; 1001 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>; 1004 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>; 1205 defm: MinMax_pats<setgt, A2_max, A2_min>; 1242 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
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D | HexagonInstrInfoV5.td | 297 defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrFloat.td | 69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>; 75 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPU64InstrInfo.td | 175 // i64 setgt/setle: 216 def : Pat<(setgt R64C:$rA, R64C:$rB), I64GTr64.Fragment>; 217 //def : Pat<(setgt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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D | SPUInstrInfo.td | 3023 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA), 3028 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>; 3039 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA), 3043 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>; 3053 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA), 3057 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>; 3068 (setgt (v8i16 VECREG:$rA), 3071 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>; 3082 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; 3085 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>; [all …]
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/external/clang/www/demo/ |
D | index.cgi | 99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaInstrInfo.td | 203 defm CMOVGT : cmov_inst<0x66, "cmovgt", CmpOpFrag<(setgt node:$R, 0)>>; 217 def : Pat<(select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE), 381 def : Pat<(setgt GPRC:$X, GPRC:$Y), (CMPLT GPRC:$Y, GPRC:$X)>; 382 def : Pat<(setgt immUExt8:$X, GPRC:$Y), (CMPLTi GPRC:$Y, immUExt8:$X)>; 736 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf), 779 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf), 909 def : Pat<(brcond (setgt GPRC:$RA, 0), bb:$DISP), 934 def : Pat<(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP), 963 def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.td | 1447 // bcond-setgt (do we need to have this pair of setlt, setgt??) 1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1580 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1780 <(setgt CPU16Regs:$lhs, -32769), 1785 // setgt 1790 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
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D | Mips64r6InstrInfo.td | 176 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
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D | MipsCondMov.td | 72 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
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D | Mips32r6InstrInfo.td | 884 def : MipsPat<(setgt VT:$lhs, VT:$rhs), 921 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
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D | Mips64InstrInfo.td | 239 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 545 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
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D | MipsInstrInfo.td | 1870 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1872 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>, 2577 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 2595 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 2619 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 1173 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1237 // setge X, 0 is canonicalized to setgt X, -1 1238 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1244 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1247 def : Pat<(setgt GRRegs:$lhs, -1),
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/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 1236 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1300 // setge X, 0 is canonicalized to setgt X, -1 1301 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1307 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1310 def : Pat<(setgt GRRegs:$lhs, -1),
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | Mips64InstrInfo.td | 161 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
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D | MipsInstrInfo.td | 731 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1002 def : Pat<(setgt RC:$lhs, RC:$rhs),
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
D | BlackfinInstrInfo.td | 582 defm SETLE : SETCC<setle, setgt, "<=">; 590 def : Pat<(setgt D:$a, D:$b), (SETLTdd D:$b, D:$a)>;
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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
D | cast.ll | 121 ; %X = setlt sbyte %c, 0 ; setgt %A, 127
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/external/llvm/test/CodeGen/Mips/ |
D | cmov.ll | 233 ; (select (setgt a, N), t, f)
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