/external/clang/test/CodeGen/ |
D | BasicInstrs.c | 19 _Bool setlt(int X, int Y) { in setlt() function
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | Mips64InstrInfo.td | 100 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 108 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 163 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
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D | MipsInstrInfo.td | 652 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 664 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 733 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
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/external/llvm/test/Transforms/LoopStrengthReduce/ |
D | dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
D | setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
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/external/llvm/test/Transforms/InstCombine/ |
D | setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
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/external/swiftshader/third_party/LLVM/test/Transforms/LoopStrengthReduce/ |
D | dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrFloat.td | 67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>; 73 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc-vaarg-agg.ll | 44 ; with an error like: Cannot select: ch = setlt [ID=6]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoVector.td | 306 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, i1>; 307 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>; 308 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, i1>; 309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>; 310 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, i1>; 311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
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D | HexagonSelectCCInfo.td | 111 // setlt-64 -> setgt-64.
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D | HexagonInstrInfoV5.td | 494 def: Pat<(i1 (setlt F32:$src1, F32:$src2)), 496 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)), 498 def: Pat<(i1 (setlt F64:$src1, F64:$src2)), 500 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
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D | HexagonInstrInfoV3.td | 148 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
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D | HexagonInstrInfo.td | 282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>; 1207 defm: MinMax_pats<setlt, A2_min, A2_max>; 1244 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>; 3984 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)), 4927 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset), 5002 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPU64InstrInfo.td | 225 // i64 setge/setlt: 253 def : I64SETCCNegCond<setlt, I64GEr64>; 254 def : I64SELECTNegCond<setlt, I64GEr64>;
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D | SPUInstrInfo.td | 3220 // For SETCC primitives not supported above (setlt, setle, setge, etc.) 3268 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>; 3269 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>; 3278 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>; 3279 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>; 3288 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>; 3289 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>; 3707 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZr16, ORr32, BRZr32>;
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.td | 1447 // bcond-setgt (do we need to have this pair of setlt, setgt??) 1470 // bcond-setlt 1473 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1478 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1631 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1767 // x > (k - 1) and then reverses the operands to use setlt. So this pattern 1801 // setlt 1803 def: SetCC_R16<setlt, SltCCRxRy16>; 1805 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
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D | Mips64InstrInfo.td | 104 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 543 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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D | MicroMipsInstrInfo.td | 682 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 705 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>; 898 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
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D | MipsInstrInfo.td | 1689 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 1706 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 1878 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1880 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>, 2593 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaInstrInfo.td | 201 defm CMOVLT : cmov_inst<0x44, "cmovlt", CmpOpFrag<(setlt node:$R, 0)>>; 221 def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE), 359 [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>; 361 [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>; 664 // [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>; 750 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf), 793 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf), 915 def : Pat<(brcond (setlt GPRC:$RA, 0), bb:$DISP), 938 def : Pat<(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP), 949 def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
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/external/clang/www/demo/ |
D | index.cgi | 99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 1183 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1234 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1241 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
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/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 1246 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1297 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1304 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
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/external/llvm/test/CodeGen/Mips/ |
D | fcmp.ll | 1060 ; The optimizers sometimes produce setlt instead of setolt/setult. 1129 ; The optimizers sometimes produce setlt instead of setolt/setult.
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