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Searched refs:shasx (Results 1 – 20 of 20) sorted by relevance

/external/valgrind/none/tests/arm/
Dv6media.stdout.exp4105 shasx r0, r1, r2 :: rd 0x0006fff3 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge…
4106 shasx r0, r1, r2 :: rd 0x000bfffd rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge…
4107 shasx r0, r1, r2 :: rd 0x0006000c rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge…
4108 shasx r0, r1, r2 :: rd 0x000b0003 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge…
4109 shasx r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge…
4110 shasx r0, r1, r2 :: rd 0x7f80407f rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge…
4111 shasx r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge…
4112 shasx r0, r1, r2 :: rd 0xbfffc000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge…
4113 shasx r0, r1, r2 :: rd 0xccf846a7 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge…
4114 shasx r0, r1, r2 :: rd 0x2bd0657a rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge…
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-a32.cc63 M(shasx) \
Dtest-assembler-cond-rd-rn-rm-t32.cc62 M(shasx) \
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-thumb2-instructions.s1776 shasx r4, r8, r2
1783 @ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4]
1786 @ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4]
Dbasic-arm-instructions.s1559 shasx r4, r8, r2
1562 @ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6]
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2211 shasx r4, r8, r2
2218 @ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4]
2221 @ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4]
Dbasic-arm-instructions.s2341 shasx r4, r8, r2
2344 @ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6]
/external/vixl/src/aarch32/
Dassembler-aarch32.h2958 void shasx(Condition cond, Register rd, Register rn, Register rm);
2959 void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); } in shasx() function
Ddisasm-aarch32.h951 void shasx(Condition cond, Register rd, Register rn, Register rm);
Dassembler-aarch32.cc8912 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) { in shasx() function in vixl::aarch32::Assembler
8929 Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm); in shasx()
Ddisasm-aarch32.cc2498 void Disassembler::shasx(Condition cond, in shasx() function in vixl::aarch32::Disassembler
21187 shasx(CurrentCond(), in DecodeT32()
63059 shasx(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
Dmacro-assembler-aarch32.h3552 shasx(cond, rd, rn, rm); in Shasx()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb2.txt1568 # CHECK: shasx r4, r8, r2
Dbasic-arm-instructions.txt1388 # CHECK: shasx r4, r8, r2
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1707 # CHECK: shasx r4, r8, r2
Dbasic-arm-instructions.txt1549 # CHECK: shasx r4, r8, r2
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td3203 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
4977 def : MnemonicAlias<"shaddsubx", "shasx">;
DARMInstrThumb2.td1970 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td3604 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
5687 def : MnemonicAlias<"shaddsubx", "shasx">;
DARMInstrThumb2.td2175 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;