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/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_tools_windows/tools/
Dsymshift.pl203 $shifted = $id + $plane * 256;
205 if ($shifted{$sym}) {
206 $otherplane = int($shifted{$sym} / 256);
209 $shifted{$sym} = $shifted;
210 $sym{$shifted} = $sym;
211 $intable{$table}{$shifted}++;
227 $shifted = $id + $plane * 256;
228 $shifted{$sym} = $shifted unless $shifted{$sym};
229 $sym{$shifted} = $sym unless $sym{$shifted};
230 $intable{$table}{$shifted}++;
[all …]
/external/unicode/
DCVTUTF7.C91 int shifted = 0, needshift = 0, done = 0; in ConvertUCS2toUTF7() local
112 if (needshift && !shifted) in ConvertUCS2toUTF7()
122 shifted = 1; in ConvertUCS2toUTF7()
125 if (shifted) in ConvertUCS2toUTF7()
159 shifted = 0; in ConvertUCS2toUTF7()
184 int shifted = 0, first = 0, wroteone = 0, base64EOF, base64value, done; in ConvertUTF7toUCS2() local
198 if (shifted) in ConvertUTF7toUCS2()
206 shifted = 0; in ConvertUTF7toUCS2()
272 if (!shifted && !done) in ConvertUTF7toUCS2()
276 shifted = 1; in ConvertUTF7toUCS2()
/external/llvm/test/CodeGen/SystemZ/
Dinsert-05.ll90 %shifted = lshr i64 %a, 1
91 %and = and i64 %shifted, 18446744069414584320
102 %shifted = lshr i64 %a, 1
103 %and = and i64 %shifted, 18446744069414584320
114 %shifted = lshr i64 %a, 1
115 %and = and i64 %shifted, 9223372032559808512
126 %shifted = lshr i64 %a, 1
127 %and = and i64 %shifted, 9223372032559808512
172 %shifted = shl i64 %a, 1
173 %and = and i64 %shifted, 4294967295
[all …]
Drnsbg-01.ll92 ; Test a case with a left shift and OR, where the OR covers all shifted bits.
116 ; shifted bits. We can't use RNSBG for the shift, but we can for the OR
141 ; Test a case with a right shift and OR, where the OR covers all the shifted
165 ; shifted bits. The shift needs to be done separately, but the OR and AND
245 ; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
Drisbg-01.ll6 ; Test an extraction of bit 0 from a right-shifted value.
26 ; Test an extraction of other bits from a right-shifted value.
46 ; Test an extraction of most bits from a right-shifted value.
90 ; Test an extraction of bits from a left-shifted value. The range should
257 ; Check that we use RISBG for shifted values even if the AND is a
433 ; Try a similar thing in which no shifted sign bits are kept.
472 ; when testing whether the shifted-in bits of the shift right were significant.
/external/llvm/test/CodeGen/AArch64/
Dbitfield.ll200 %shifted = lshr i32 %fields, 23
201 %masked = and i32 %shifted, 7
209 %shifted = lshr i64 %fields, 25
210 %masked = and i64 %shifted, 1023
219 %shifted = shl i32 %fields, 23
220 %extended = ashr i32 %shifted, 29
229 %shifted = shl i64 %fields, 1
230 %extended = ashr i64 %shifted, 1
Darm64-misched-forwarding-A53.ll4 ; For Cortex-A53, shiftable operands that are not actually shifted
Daddsub.ll56 ; Add 12-bit immediates, shifted left by 12 bits
90 ; Subtract 12-bit immediates, shifted left by 12 bits
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_format_aos.c154 LLVMValueRef shifted, casted, scaled, masked; in lp_build_unpack_arith_rgba_aos() local
229 shifted = LLVMBuildLShr(builder, packed, LLVMConstVector(shifts, 4), ""); in lp_build_unpack_arith_rgba_aos()
230 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), ""); in lp_build_unpack_arith_rgba_aos()
271 LLVMValueRef shifted, casted, scaled, unswizzled; in lp_build_pack_rgba_aos() local
335 shifted = LLVMBuildShl(builder, casted, LLVMConstVector(shifts, 4), ""); in lp_build_pack_rgba_aos()
340 LLVMValueRef component = LLVMBuildExtractElement(builder, shifted, in lp_build_pack_rgba_aos()
Dlp_bld_swizzle.c403 LLVMValueRef shifted; in lp_build_swizzle_aos() local
411 shifted = LLVMBuildShl(builder, masked, in lp_build_swizzle_aos()
414 shifted = LLVMBuildLShr(builder, masked, in lp_build_swizzle_aos()
417 shifted = masked; in lp_build_swizzle_aos()
420 res = LLVMBuildOr(builder, res, shifted, ""); in lp_build_swizzle_aos()
Dlp_bld_conv.c113 …LLVMValueRef shifted = LLVMBuildBitCast(builder, LLVMBuildShl(builder, expmant, i32_13, ""),… in lp_build_half_to_float() local
116 …LLVMValueRef scaled = LLVMBuildBitCast(builder, LLVMBuildFMul(builder, shifted, f32_magic, … in lp_build_half_to_float()
591 LLVMValueRef shifted; in lp_build_conv() local
594 shifted = LLVMBuildAShr(builder, tmp[i], shift, ""); in lp_build_conv()
596 shifted = LLVMBuildLShr(builder, tmp[i], shift, ""); in lp_build_conv()
598 tmp[i] = LLVMBuildSub(builder, tmp[i], shifted, ""); in lp_build_conv()
/external/llvm/test/CodeGen/X86/
Dtrunc-to-bool.ll15 %shifted = ashr i32 %val, %mask
16 %anded = and i32 %shifted, 1
Durem-power-of-two.ll17 ; A left-shifted power-of-2 divisor. Use a weird type for wider coverage.
34 ; FIXME: A logically right-shifted sign bit is a power-of-2 or UB.
Dsext-load.ll17 ; preserved even when removing shifted-out low bits.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dtrunc-to-bool.ll15 %shifted = ashr i32 %val, %mask
16 %anded = and i32 %shifted, 1
/external/icu/icu4c/source/data/coll/
Dth.txt9 "[alternate shifted]"
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-MOVs-arm.txt13 # A8.6.98 MOV (shifted register), and
/external/libavc/common/arm/
Dih264_intra_pred_luma_8x8_a9q.s468 @ q1 = q0 shifted to left once
469 @ q2 = q1 shifted to left once
560 @ q1 = q0 shifted to left once
561 @ q2 = q1 shifted to left once
650 @ q1 = q0 shifted to left once
651 @ q2 = q1 shifted to left once
770 @ q1 = q0 shifted to left once
771 @ q2 = q1 shifted to left once
/external/skia/src/opts/
DSkBitmapProcState_opts_SSE2.cpp105 __m128i shifted = _mm_shuffle_epi32(sum, 0xEE); in S32_opaque_D32_filter_DX_SSE2() local
108 sum = _mm_add_epi16(sum, shifted); in S32_opaque_D32_filter_DX_SSE2()
215 __m128i shifted = _mm_shuffle_epi32(sum, 0xEE); in S32_alpha_D32_filter_DX_SSE2() local
218 sum = _mm_add_epi16(sum, shifted); in S32_alpha_D32_filter_DX_SSE2()
/external/autotest/client/deps/glbench/src/
Dyuv2rgb_1.glslf123 * and shifted down 2/3 to map from the U texels, and scaled by 1/6
124 * and shifted down 5/6 to map from the V texels. To map from U or V
125 * texels the 'x' coordinate is scaled by 1/2 always and shifted right
/external/icu/icu4c/source/test/perf/collationperf/
DMakefile.in61 … ./$(TARGET) -loop 200 -file $(top_srcdir)/extra/uconv/samples/utf8/utf-8-demo.txt -keygen -shifted
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUNodes.td94 // Vector rotate left, bits shifted out of the left are rotated in on the right
104 // Shift entire quad left by bytes/bits. Zeros are shifted in on the right
/external/proguard/docs/manual/
Dstyle.css48 .shifted li
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dlshr-phi.ll6 ; bits in the operand which might be non-zero will be shifted
/external/llvm/test/Transforms/InstCombine/
Dlshr-phi.ll6 ; bits in the operand which might be non-zero will be shifted

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