Home
last modified time | relevance | path

Searched refs:shrn2 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll10 ; CHECK-NEXT: shrn2.16b v0, v1, #5
26 ; CHECK-NEXT: shrn2.8h v0, v1, #5
42 ; CHECK-NEXT: shrn2.4s v0, v1, #5
71 ; CHECK-NEXT: shrn2.8h v0, v2, #5
Dneon-diagnostics.ll16 ; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
Darm64-neon-simd-shift.ll263 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
275 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
287 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
299 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
311 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
323 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
Darm64-vshift.ll706 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
717 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
728 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s265 shrn2 v0.16b, v1.8h, #3
266 shrn2 v0.8h, v1.4s, #3
267 shrn2 v0.4s, v1.2d, #3
Darm64-advsimd.s1474 shrn2.16b v0, v0, #2
1476 shrn2.8h v0, v0, #4
1478 shrn2.4s v0, v0, #6
1646 ; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
1648 ; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
1650 ; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
1806 shrn2 v8.16b, v9.8h, #2
1808 shrn2 v6.8h, v7.4s, #4
1810 shrn2 v4.4s, v5.2d, #6
1876 ; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
[all …]
Dneon-diagnostics.s1810 shrn2 v0.16b, v1.8h, #17
1811 shrn2 v0.8h, v1.4s, #33
1812 shrn2 v0.4s, v1.2d, #65
/external/libjpeg-turbo/simd/
Djsimd_arm64_neon.S391 …shrn2 v2.8h, v19.4s, #16 /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS+P…
392 …shrn2 v9.8h, v21.4s, #16 /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS+P…
393 …shrn2 v3.8h, v23.4s, #16 /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS+P…
394 …shrn2 v8.8h, v25.4s, #16 /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS+P…
395 …shrn2 v4.8h, v27.4s, #16 /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS+P…
396 …shrn2 v7.8h, v29.4s, #16 /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS+P…
397 …shrn2 v5.8h, v15.4s, #16 /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS+P…
398 …shrn2 v6.8h, v17.4s, #16 /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS+P…
1983 shrn2 v22.8h, v26.4s, #16
1984 shrn2 v24.8h, v30.4s, #16
[all …]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s525 shrn2 v0.8h, v23.4s, #1 //i4_value = (x3 + x2) >> 1;
527 shrn2 v1.8h, v25.4s, #1 //i4_value = (x3 - x2) >> 1;
/external/vixl/src/aarch64/
Dlogic-aarch64.cc2576 LogicVRegister Simulator::shrn2(VectorFormat vform, in shrn2() function in vixl::aarch64::Simulator
2727 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
3382 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
3426 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
Dsimulator-aarch64.h2590 LogicVRegister shrn2(VectorFormat vform,
Dassembler-aarch64.h2274 void shrn2(const VRegister& vd, const VRegister& vn, int shift);
Dmacro-assembler-aarch64.h2410 V(shrn2, Shrn2) \
Dsimulator-aarch64.cc5062 shrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
Dassembler-aarch64.cc3761 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) { in shrn2() function in vixl::aarch64::Assembler
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt957 # CHECK: shrn2 v0.16b, v1.8h, #3
958 # CHECK: shrn2 v0.8h, v1.4s, #3
959 # CHECK: shrn2 v0.4s, v1.2d, #3
Darm64-advsimd.txt2049 # CHECK: shrn2.16b v0, v0, #0x6
2051 # CHECK: shrn2.8h v0, v0, #0xc
2053 # CHECK: shrn2.4s v0, v0, #0x1a
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1192 0x~~~~~~~~~~~~~~~~ 4f0d87c5 shrn2 v5.16b, v30.8h, #3
1193 0x~~~~~~~~~~~~~~~~ 4f3f8438 shrn2 v24.4s, v1.2d, #1
1194 0x~~~~~~~~~~~~~~~~ 4f1085c5 shrn2 v5.8h, v14.4s, #16
Dlog-disasm1192 0x~~~~~~~~~~~~~~~~ 4f0d87c5 shrn2 v5.16b, v30.8h, #3
1193 0x~~~~~~~~~~~~~~~~ 4f3f8438 shrn2 v24.4s, v1.2d, #1
1194 0x~~~~~~~~~~~~~~~~ 4f1085c5 shrn2 v5.8h, v14.4s, #16
Dlog-all3207 0x~~~~~~~~~~~~~~~~ 4f0d87c5 shrn2 v5.16b, v30.8h, #3
3209 0x~~~~~~~~~~~~~~~~ 4f3f8438 shrn2 v24.4s, v1.2d, #1
3211 0x~~~~~~~~~~~~~~~~ 4f1085c5 shrn2 v5.8h, v14.4s, #16
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1426 __ shrn2(v5.V16B(), v30.V8H(), 3); in GenerateTestSequenceNEON() local
1427 __ shrn2(v24.V4S(), v1.V2D(), 1); in GenerateTestSequenceNEON() local
1428 __ shrn2(v5.V8H(), v14.V4S(), 16); in GenerateTestSequenceNEON() local
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27479 shrn2 v4.4s, v29.2d, #1 05a003fc900f175872e9f9c702e3af02 47b46e2da3006c22acb82c8f0707bcd1 d180…
27480 shrn2 v4.4s, v29.2d, #32 ce9d16cc51acf288c7fa0a9e80db4e19 e6577d7b0cd1336853c02e8cdb72ea16 e65…
27483 shrn2 v4.8h, v29.4s, #1 37dd74eff68b2b92750df7e73f159295 37d4bb79ebe9d590c97f9f3d4de279ea 5dbc…
27484 shrn2 v4.8h, v29.4s, #16 63d3f58415774aa77a78bbbb98ac6a3a bf4ecdb9d7061609e6002aa6612a564c bf4…
27487 shrn2 v4.16b, v29.8h, #1 5c2be056dd758c1dfb879d9518351b70 05a56feb04e721cba2ccf63cd0e241d7 d2f5…
27488 shrn2 v4.16b, v29.8h, #8 d2d9c4bfdf8d8646d64b49b512890211 dc35fbad7baef126dc43bfdf6ba52443 dcfb…
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3119 void shrn2(const VRegister& vd,