| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | add.ll | 108 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
115 ; MM32: sltu $[[T0:[0-9]+]], $3, $7
131 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
137 ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
140 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
147 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
153 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
157 ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
162 ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
169 ; MM64: sltu $[[T0:[0-9]+]], $3, $7
[all …]
|
| D | sub.ll | 103 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
118 ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
125 ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
128 ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
134 ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
141 ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
144 ; GP32-MM: sltu $[[T2]], $7, $[[T4]]
150 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
|
| D | select-int.ll | 216 ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
225 ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
240 ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
251 ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
264 ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
|
| /external/llvm/test/MC/Mips/ |
| D | macro-bcc-imm.s | 23 # ALL: sltu $1, $6, $1
27 # ALL: sltu $1, $1, $6
31 # ALL: sltu $1, $6, $1
35 # ALL: sltu $1, $1, $6
55 # ALL: sltu $1, $6, $1
59 # ALL: sltu $1, $1, $6
63 # ALL: sltu $1, $6, $1
67 # ALL: sltu $1, $1, $6
|
| D | instalias-imm-expanding.s | 209 sltu $4, $5, -0x80000000
211 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
212 sltu $4, $5, -0x8001
215 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
216 sltu $4, $5, -0x8000
218 sltu $4, $5, 0
220 sltu $4, $5, 0xFFFF
222 sltu $4, $5, 0x10000
224 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
225 sltu $4, $5, 0xFFFFFFFF
|
| D | branch-pseudos.s | 31 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
36 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
74 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
79 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
123 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
128 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
171 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
176 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
282 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
287 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
[all …]
|
| D | mips_gprel16.s | 33 sltu $2, $zero, $1
57 sltu $2, $zero, $1
|
| D | micromips-alu-instructions.s | 24 # CHECK-EL: sltu $3, $3, $5 # encoding: [0xa3,0x00,0x90,0x1b]
67 # CHECK-EB: sltu $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x90]
108 sltu $3, $3, $5
|
| D | mips64-alu-instructions.s | 25 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
53 sltu $3, $3, $5
|
| D | mips-alu-instructions.s | 27 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
58 sltu $3, $3, $5
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | sel1.ll | 10 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
27 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
44 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
59 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
75 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
91 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
|
| D | icmpa.ll | 47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
|
| /external/llvm/test/CodeGen/Mips/ |
| D | llcarry.ll | 17 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| D | 2008-06-05-Carry.ll | 6 ; CHECK: sltu
17 ; CHECK: sltu
|
| D | madd-msub.ll | 28 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
74 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
112 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
153 ; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
200 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
239 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
|
| D | setcc-se.ll | 16 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
109 ; CHECK: sltu ${{[0-9]+}}
142 ; CHECK: sltu ${{[0-9]+}}
|
| D | cmov.ll | 396 ; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5
405 ; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5
441 ; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5
450 ; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5
582 ; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
588 ; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4
597 ; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
603 ; 64-CMP-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
657 ; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4
664 ; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4
[all …]
|
| D | setne.ll | 17 ; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
|
| D | setult.ll | 18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| D | setugt.ll | 18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 785 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
786 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
787 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
788 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
789 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
790 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
791 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
792 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
793 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
794 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32-BE | 785 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
786 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
787 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
788 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
789 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
790 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
791 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
792 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
793 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
794 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-LE | 1263 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
1264 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
1265 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
1266 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
1267 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
1268 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1269 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1270 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1271 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
1272 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
|
| D | MIPS32int.stdout.exp-mips32r2-BE | 1263 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
1264 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
1265 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
1266 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
1267 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
1268 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1269 sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1270 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1271 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
1272 sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 97 … sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
98 … sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
|