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Searched refs:smulwb (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dsmul.ll109 ; CHECK: smulwb
122 ; CHECK: smulwb
/external/arm-neon-tests/
Dref_dsp.c391 sres = smulwb(svar1, svar2); in exec_dsp()
398 sres = smulwb(svar1, svar2); in exec_dsp()
Dref-rvct-all.txt8034 smulwb(0x12345678, 0x12345678) = 0x6261d94
8036 smulwb(0xf123f456, 0xf123f456) = 0xad52a0
/external/valgrind/none/tests/arm/
Dv6media.stdout.exp379 smulwb r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00020004, carryin 0, cpsr 0x00000000 g…
380 smulwb r0, r1, r2 :: rd 0x00000004 rm 0x00010003, rn 0x47ff0004, carryin 0, cpsr 0x00000000 g…
381 smulwb r0, r1, r2 :: rd 0xfffe0004 rm 0x80010003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 g…
382 smulwb r0, r1, r2 :: rd 0x0001fffc rm 0x7fff0003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 g…
383 smulwb r0, r1, r2 :: rd 0xfffffffc rm 0xffff0003, rn 0xffff0004, carryin 0, cpsr 0x00000000 g…
384 smulwb r0, r1, r2 :: rd 0x05ec94f3 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 g…
385 smulwb r0, r1, r2 :: rd 0xfefee815 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 g…
386 smulwb r0, r1, r2 :: rd 0x000c1f84 rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 g…
387 smulwb r0, r1, r2 :: rd 0xfe0bd12f rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 g…
388 smulwb r0, r1, r2 :: rd 0xf17bdc1c rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 g…
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-a32.cc75 M(smulwb) \
Dtest-assembler-cond-rd-rn-rm-t32.cc74 M(smulwb) \
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1810 smulwb r3, r9, r0
1813 @ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1]
Dbasic-thumb2-instructions.s2068 smulwb r3, r9, r0
2074 @ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3152 void smulwb(Condition cond, Register rd, Register rn, Register rm);
3153 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } in smulwb() function
Ddisasm-aarch32.h1053 void smulwb(Condition cond, Register rd, Register rn, Register rm);
Dassembler-aarch32.cc9722 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) { in smulwb() function in vixl::aarch32::Assembler
9739 Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm); in smulwb()
Ddisasm-aarch32.cc2836 void Disassembler::smulwb(Condition cond, in smulwb() function in vixl::aarch32::Disassembler
22096 smulwb(CurrentCond(), in DecodeT32()
57052 smulwb(condition, in DecodeA32()
Dmacro-assembler-aarch32.h4139 smulwb(cond, rd, rn, rm); in Smulwb()
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2583 smulwb r3, r9, r0
2586 @ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1]
Dbasic-thumb2-instructions.s2503 smulwb r3, r9, r0
2509 @ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1639 # CHECK: smulwb r3, r9, r0
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1791 # CHECK: smulwb r3, r9, r0