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/external/llvm/test/CodeGen/AArch64/
Darm64-neon-v8.1a.ll5 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
6 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
7 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
8 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
9 declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32)
10 declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16)
32 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
34 ; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.4h
42 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
44 ; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.8h
[all …]
Darm64-neon-mul-div.ll737 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
738 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
739 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
740 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
744 %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
745 ; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
751 %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
752 ; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
758 %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
759 ; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
[all …]
Darm64-vmul.ll174 ;CHECK: sqrdmulh.4h
177 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
183 ;CHECK: sqrdmulh.8h
186 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
192 ;CHECK: sqrdmulh.2s
195 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
201 ;CHECK: sqrdmulh.4s
204 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
210 ;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
213 %tmp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
[all …]
Darm64-neon-2velem.ll9 declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
11 declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
13 declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
15 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
1373 …%vqrdmulh2.i = tail call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %a, <4 x i16> %shuf…
1383 …%vqrdmulh2.i = tail call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %a, <8 x i16> %shuf…
1393 …%vqrdmulh2.i = tail call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %a, <2 x i32> %shuf…
1403 …%vqrdmulh2.i = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %a, <4 x i32> %shuf…
2752 …%vqrdmulh2.i = tail call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %a, <4 x i16> %shuf…
2762 …%vqrdmulh2.i = tail call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %a, <8 x i16> %shuf…
[all …]
/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s43 sqrdmulh h31, h30, v14.h[2]
44 sqrdmulh h1, h1, v1.h[4]
45 sqrdmulh h21, h22, v15.h[7]
46 sqrdmulh s5, s6, v7.s[2]
47 sqrdmulh s20, s26, v27.s[1]
Dneon-mul-div-instructions.s68 sqrdmulh v2.4h, v25.4h, v3.4h
69 sqrdmulh v12.8h, v5.8h, v13.8h
70 sqrdmulh v3.2s, v1.2s, v30.2s
Darm64-v128_lo-diagnostics.s4 sqrdmulh v0.8h, v1.8h, v16.h[0]
7 sqrdmulh h0, h1, v16.h[0]
Dneon-scalar-mul.s19 sqrdmulh h10, h11, h12
20 sqrdmulh s20, s21, s2
Dneon-2velem.s275 sqrdmulh v0.4h, v1.4h, v2.h[2]
276 sqrdmulh v0.8h, v1.8h, v2.h[2]
277 sqrdmulh v0.2s, v1.2s, v2.s[2]
278 sqrdmulh v0.2s, v1.2s, v22.s[2]
279 sqrdmulh v0.4s, v1.4s, v2.s[2]
280 sqrdmulh v0.4s, v1.4s, v22.s[2]
Dneon-diagnostics.s901 sqrdmulh h10, s11, h12
902 sqrdmulh s20, h21, s2
1261 sqrdmulh v2.2s, v25.4s, v3.4s
1262 sqrdmulh v12.16b, v5.16b, v13.16b
1263 sqrdmulh v3.4h, v1.4h, v30.2d
3671 sqrdmulh v0.4h, v1.4h, v2.h[8]
3672 sqrdmulh v0.4h, v1.4h, v16.h[2]
3673 sqrdmulh v0.8h, v1.8h, v2.h[8]
3674 sqrdmulh v0.8h, v1.8h, v16.h[2]
3675 sqrdmulh v0.2s, v1.2s, v2.s[4]
[all …]
Darm64-advsimd.s348 sqrdmulh.4h v0, v0, v0
419 ; CHECK: sqrdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x2e]
1149 sqrdmulh.h h0, h0, v0[7]
1150 sqrdmulh.s s0, s0, v0[3]
1167 ; CHECK: sqrdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xd8,0x70,0x5f]
1168 ; CHECK: sqrdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x5f]
1257 sqrdmulh.4h v0, v0, v0[0]
1258 sqrdmulh.8h v0, v0, v0[1]
1259 sqrdmulh.2s v0, v0, v0[2]
1260 sqrdmulh.4s v0, v0, v0[3]
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt659 # CHECK: sqrdmulh v31.4h, v3.4h, v13.4h
660 # CHECK: sqrdmulh v0.8h, v10.8h, v20.8h
1483 # CHECK: sqrdmulh h10, h11, h12
1484 # CHECK: sqrdmulh s20, s21, s2
2455 # CHECK: sqrdmulh h7, h1, v14.h[0]
2456 # CHECK: sqrdmulh h7, h15, v8.h[1]
2457 # CHECK: sqrdmulh h7, h15, v8.h[2]
2458 # CHECK: sqrdmulh h7, h15, v8.h[3]
2459 # CHECK: sqrdmulh h7, h15, v8.h[4]
2460 # CHECK: sqrdmulh h7, h15, v8.h[5]
[all …]
Darm64-advsimd.txt331 # CHECK: sqrdmulh.4h v0, v0, v0
1614 # CHECK: sqrdmulh.h h0, h0, v0[7]
1615 # CHECK: sqrdmulh.s s0, s0, v0[3]
1742 # CHECK: sqrdmulh.4h v0, v0, v0[0]
1743 # CHECK: sqrdmulh.8h v0, v0, v0[1]
1744 # CHECK: sqrdmulh.2s v0, v0, v0[2]
1745 # CHECK: sqrdmulh.4s v0, v0, v0[3]
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1359 0x~~~~~~~~~~~~~~~~ 7e60b707 sqrdmulh h7, h24, h0
1360 0x~~~~~~~~~~~~~~~~ 5f64d86e sqrdmulh h14, h3, v4.h[6]
1361 0x~~~~~~~~~~~~~~~~ 7eb8b67b sqrdmulh s27, s19, s24
1362 0x~~~~~~~~~~~~~~~~ 5f84d2bf sqrdmulh s31, s21, v4.s[0]
1363 0x~~~~~~~~~~~~~~~~ 2ea1b732 sqrdmulh v18.2s, v25.2s, v1.2s
1364 0x~~~~~~~~~~~~~~~~ 0f8dd0b6 sqrdmulh v22.2s, v5.2s, v13.s[0]
1365 0x~~~~~~~~~~~~~~~~ 2e69b716 sqrdmulh v22.4h, v24.4h, v9.4h
1366 0x~~~~~~~~~~~~~~~~ 0f6cd84d sqrdmulh v13.4h, v2.4h, v12.h[6]
1367 0x~~~~~~~~~~~~~~~~ 6ea2b769 sqrdmulh v9.4s, v27.4s, v2.4s
1368 0x~~~~~~~~~~~~~~~~ 4fa7d2e3 sqrdmulh v3.4s, v23.4s, v7.s[1]
[all …]
Dlog-disasm1359 0x~~~~~~~~~~~~~~~~ 7e60b707 sqrdmulh h7, h24, h0
1360 0x~~~~~~~~~~~~~~~~ 5f64d86e sqrdmulh h14, h3, v4.h[6]
1361 0x~~~~~~~~~~~~~~~~ 7eb8b67b sqrdmulh s27, s19, s24
1362 0x~~~~~~~~~~~~~~~~ 5f84d2bf sqrdmulh s31, s21, v4.s[0]
1363 0x~~~~~~~~~~~~~~~~ 2ea1b732 sqrdmulh v18.2s, v25.2s, v1.2s
1364 0x~~~~~~~~~~~~~~~~ 0f8dd0b6 sqrdmulh v22.2s, v5.2s, v13.s[0]
1365 0x~~~~~~~~~~~~~~~~ 2e69b716 sqrdmulh v22.4h, v24.4h, v9.4h
1366 0x~~~~~~~~~~~~~~~~ 0f6cd84d sqrdmulh v13.4h, v2.4h, v12.h[6]
1367 0x~~~~~~~~~~~~~~~~ 6ea2b769 sqrdmulh v9.4s, v27.4s, v2.4s
1368 0x~~~~~~~~~~~~~~~~ 4fa7d2e3 sqrdmulh v3.4s, v23.4s, v7.s[1]
[all …]
Dlog-all3541 0x~~~~~~~~~~~~~~~~ 7e60b707 sqrdmulh h7, h24, h0
3543 0x~~~~~~~~~~~~~~~~ 5f64d86e sqrdmulh h14, h3, v4.h[6]
3545 0x~~~~~~~~~~~~~~~~ 7eb8b67b sqrdmulh s27, s19, s24
3547 0x~~~~~~~~~~~~~~~~ 5f84d2bf sqrdmulh s31, s21, v4.s[0]
3549 0x~~~~~~~~~~~~~~~~ 2ea1b732 sqrdmulh v18.2s, v25.2s, v1.2s
3551 0x~~~~~~~~~~~~~~~~ 0f8dd0b6 sqrdmulh v22.2s, v5.2s, v13.s[0]
3553 0x~~~~~~~~~~~~~~~~ 2e69b716 sqrdmulh v22.4h, v24.4h, v9.4h
3555 0x~~~~~~~~~~~~~~~~ 0f6cd84d sqrdmulh v13.4h, v2.4h, v12.h[6]
3557 0x~~~~~~~~~~~~~~~~ 6ea2b769 sqrdmulh v9.4s, v27.4s, v2.4s
3559 0x~~~~~~~~~~~~~~~~ 4fa7d2e3 sqrdmulh v3.4s, v23.4s, v7.s[1]
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1593 __ sqrdmulh(h7, h24, h0); in GenerateTestSequenceNEON() local
1594 __ sqrdmulh(h14, h3, v4.H(), 6); in GenerateTestSequenceNEON() local
1595 __ sqrdmulh(s27, s19, s24); in GenerateTestSequenceNEON() local
1596 __ sqrdmulh(s31, s21, v4.S(), 0); in GenerateTestSequenceNEON() local
1597 __ sqrdmulh(v18.V2S(), v25.V2S(), v1.V2S()); in GenerateTestSequenceNEON() local
1598 __ sqrdmulh(v22.V2S(), v5.V2S(), v13.S(), 0); in GenerateTestSequenceNEON() local
1599 __ sqrdmulh(v22.V4H(), v24.V4H(), v9.V4H()); in GenerateTestSequenceNEON() local
1600 __ sqrdmulh(v13.V4H(), v2.V4H(), v12.H(), 6); in GenerateTestSequenceNEON() local
1601 __ sqrdmulh(v9.V4S(), v27.V4S(), v2.V4S()); in GenerateTestSequenceNEON() local
1602 __ sqrdmulh(v3.V4S(), v23.V4S(), v7.S(), 1); in GenerateTestSequenceNEON() local
[all …]
Dtest-simulator-aarch64.cc4134 DEFINE_TEST_NEON_3SAME_HS(sqrdmulh, Basic)
4179 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqrdmulh, Basic)
4436 DEFINE_TEST_NEON_BYELEMENT(sqrdmulh, Basic, Basic, Basic)
4453 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqrdmulh, Basic, Basic, Basic)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28031 sqrdmulh s0, s1, v2.s[1] aaf5bbd53d55b0dd75b6dd26e2c63865 02d429c264db9cf6a30ccb687eef96d5 f633…
28032 sqrdmulh s0, s1, v2.s[3] 379cf43e8743df8af1f360026ee5f41e 49a69c86e32553a3cc7a0d3e869493b2 483e…
28033 sqrdmulh h0, h1, v2.h[2] b5f698f5099c8fa54f23cca734f5ebae 7ad8b580a5baae76b89c7d43af61cc40 a705…
28034 sqrdmulh h0, h1, v2.h[7] 8f5d3226c1e25f210d8a0f8667ab4927 48331506c1d325ff6b65772d3614878b 45e0…
28044 sqrdmulh v0.4s, v1.4s, v2.s[1] 8ca44b9ff998289fde39d478daba217a 014ffde2fdf82bffb09f75dc69cf164c…
28045 sqrdmulh v0.4s, v1.4s, v2.s[3] d7cecca454409260f3da8a20cac1672d 1dc388f4e43c85b1d182248d6ad44316…
28046 sqrdmulh v0.2s, v1.2s, v2.s[1] de83c9ce6133eaf2487e797da2fc8832 0b6f35a8349912d28957f3b1471ad20f…
28047 sqrdmulh v0.2s, v1.2s, v2.s[3] cfe86772af64f8965b32c43d457766eb 91cb8a92d43265a2a488f9d703a92b99…
28048 sqrdmulh v0.8h, v1.8h, v2.h[2] 6cc384c71bf05b30cc277c24a8bfa360 7a76f4619772caad3c678e57e12503c2…
28049 sqrdmulh v0.8h, v1.8h, v2.h[7] e792ee193b925dd55f4a005ab5c52d20 d743d12d441496e0cce15463deed2e96…
[all …]
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc3464 sqrdmulh(vf, rd, rn, rm); in VisitNEON3Same()
3774 Op = &Simulator::sqrdmulh; in VisitNEONByIndexedElement()
4677 sqrdmulh(vf, rd, rn, rm); in VisitNEONScalar3Same()
4747 Op = &Simulator::sqrdmulh; in VisitNEONScalarByIndexedElement()
Dlogic-aarch64.cc1116 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, in sqrdmulh() function in vixl::aarch64::Simulator
1123 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqrdmulh()
3327 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, in sqrdmulh() function in vixl::aarch64::Simulator
3361 return sqrdmulh(vform, dst, src1, src2, false); in sqdmulh()
Dsimulator-aarch64.h2103 LogicVRegister sqrdmulh(VectorFormat vform,
2650 LogicVRegister sqrdmulh(VectorFormat vform,
Dassembler-aarch64.h2412 void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2421 void sqrdmulh(const VRegister& vd,
Dmacro-assembler-aarch64.h2197 V(sqrdmulh, Sqrdmulh) \
2371 V(sqrdmulh, Sqrdmulh) \
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3479 void sqrdmulh(const VRegister& vd,
3489 void sqrdmulh(const VRegister& vd,

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