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/external/skia/src/opts/
DSkOpts_ssse3.cpp9 #define SK_OPTS_NS ssse3
16 create_xfermode = ssse3::create_xfermode; in Init_ssse3()
17 blit_mask_d32_a8 = ssse3::blit_mask_d32_a8; in Init_ssse3()
19 RGBA_to_BGRA = ssse3::RGBA_to_BGRA; in Init_ssse3()
20 RGBA_to_rgbA = ssse3::RGBA_to_rgbA; in Init_ssse3()
21 RGBA_to_bgrA = ssse3::RGBA_to_bgrA; in Init_ssse3()
22 RGB_to_RGB1 = ssse3::RGB_to_RGB1; in Init_ssse3()
23 RGB_to_BGR1 = ssse3::RGB_to_BGR1; in Init_ssse3()
24 gray_to_RGB1 = ssse3::gray_to_RGB1; in Init_ssse3()
25 grayA_to_RGBA = ssse3::grayA_to_RGBA; in Init_ssse3()
[all …]
Dopts_check_x86.cpp42 const bool ssse3 = SkCpu::Supports(SkCpu::SSSE3); in platformProcs() local
46 if (ssse3) { in platformProcs()
52 if (ssse3) { in platformProcs()
56 if (ssse3) { in platformProcs()
62 if (ssse3) { in platformProcs()
/external/llvm/test/CodeGen/X86/
Dssse3-intrinsics-x86.ll1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+ssse3 | FileCheck %s
5 %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
8 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
13 %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
16 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
21 %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
24 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
29 …%res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#us…
32 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
37 …%res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#u…
[all …]
Dssse3-intrinsics-fast-isel.ll2 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix…
3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-pref…
5 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/ssse3-builtins.c
18 %call = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %arg)
22 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
35 %call = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %arg)
39 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
52 %call = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %arg)
56 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
108 %call = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %arg0, <8 x i16> %arg1)
[all …]
Dvector-shuffle-combining-ssse3.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-pre…
10 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
22 …%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 0, i8 0, i…
23 …%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 128, i8 0,…
24 …%res2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res1, <16 x i8> <i8 0, i8 1, i8 128,…
38 …%res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 128, i8 1, i…
39 …%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 2, i8 4, i…
54 …%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8…
71 …%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8…
88 …%2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8…
[all …]
Dpshufb-mask-comments.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s
11 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8…
22 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 15, i8 0, i8 0, i…
33 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8…
50 %4 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %3)
69 %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %1)
86 %4 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %3)
90 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
Dx86-fold-pshufb.ll2 ; RUN: llc -relocation-model=pic -march=x86-64 -mtriple=x86_64-unknown-unknown -mattr=+ssse3 < %s |…
3 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-unknown -mattr=+ssse3 < %s | FileCheck %s
14 …%0 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 0…
30 …%0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 …
35 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
Dstack-folding-mmx.ll1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+ssse3 | FileCheck %s
66 %2 = call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %a0) nounwind readnone
69 declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
75 %2 = call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %a0) nounwind readnone
78 declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
84 %2 = call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %a0) nounwind readnone
87 declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
291 %2 = call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %a, x86_mmx %b) nounwind readnone
294 declare x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx, x86_mmx) nounwind readnone
300 %2 = call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %a, x86_mmx %b) nounwind readnone
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Dv4i32load-crash.ll1 ; RUN: llc --march=x86 --mcpu=x86-64 --mattr=ssse3 < %s
2 ; RUN: llc --march=x86-64 --mcpu=x86-64 --mattr=ssse3 < %s
Dmmx-intrinsics.ll1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix…
3 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-pre…
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
1206 declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
1214 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %1) nounwind readnone
1221 declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
1229 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %1) nounwind readnone
1236 declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
1244 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %1) nounwind readnone
[all …]
Dmemset64-on-x86-32.ll3 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=SLOW_32
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=SLOW_64
/external/llvm/test/Bitcode/
Dssse3_palignr.ll9 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i…
18 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> …
24 declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
30 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>>…
40 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> …
50 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> …
60 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i…
65 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
71 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i…
80 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i…
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dpalignr-2.ll1 ; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s
12 …%0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind …
17 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
25 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind …
Dmmx-builtins.ll1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3 | FileCheck %s
3 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
12 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
1108 declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
1115 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %1) nounwind readnone
1122 declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
1129 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %1) nounwind readnone
1136 declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
1143 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %1) nounwind readnone
1150 declare x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx, x86_mmx) nounwind readnone
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dvariance_sse2.c323 DECLS(ssse3, ssse3);
375 FNS(ssse3, ssse3);
393 DECLS(ssse3, ssse3);
446 FNS(ssse3, ssse3);
Dsubpel_variance_sse2.asm106 %if cpuflag(ssse3)
113 ; FIXME(rbultje) only bilinear filters use >8 registers, and ssse3 only uses
409 %if cpuflag(ssse3)
455 %if cpuflag(ssse3)
703 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
890 %if cpuflag(ssse3)
932 %if cpuflag(ssse3)
1003 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
1206 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
/external/skia/bench/
Dpack_int_uint16_t_Bench.cpp75 __m128i ssse3(__m128i x) { in ssse3() function
81 DEF_BENCH( return new pack_int_uint16_t_Bench<ssse3>("ssse3"); )
/external/flac/libFLAC/
Dcpu.c52 info->ia32.ssse3 = false; in disable_sse()
180 info->ia32.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false; in FLAC__cpu_info()
199 fprintf(stderr, " SSSE3 ...... %c\n", info->ia32.ssse3 ? 'Y' : 'n'); in FLAC__cpu_info()
358 info->x86.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false; in FLAC__cpu_info()
372 fprintf(stderr, " SSSE3 ...... %c\n", info->x86.ssse3 ? 'Y' : 'n'); in FLAC__cpu_info()
/external/flac/libFLAC/include/private/
Dcpu.h127 FLAC__bool ssse3; member
139 FLAC__bool ssse3; member
/external/llvm/test/Transforms/InstCombine/
Dx86-pshufb.ll10 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
28 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
48 %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> zeroinitializer)
74 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 1, i…
83 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
92 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
101 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
110 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
119 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 -…
183 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
[all …]
/external/toolchain-utils/crosperf/test_cache/test_puretelemetry_input/
Dmachine.txt1 …ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave lahf_lm arat epb xs…
/external/toolchain-utils/crosperf/test_cache/test_input/
Dmachine.txt1 …ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave lahf_lm arat epb xs…
/external/valgrind/none/tests/amd64/
Dssse3_misaligned.vgtest2 prereq: ../../../tests/x86_amd64_features amd64-ssse3
/external/clang/include/clang/Basic/
DBuiltinsX86.def176 TARGET_BUILTIN(__builtin_ia32_pabsb, "V8cV8c", "", "ssse3")
177 TARGET_BUILTIN(__builtin_ia32_pabsd, "V2iV2i", "", "ssse3")
178 TARGET_BUILTIN(__builtin_ia32_pabsw, "V4sV4s", "", "ssse3")
179 TARGET_BUILTIN(__builtin_ia32_palignr, "V8cV8cV8cIc", "", "ssse3")
180 TARGET_BUILTIN(__builtin_ia32_phaddd, "V2iV2iV2i", "", "ssse3")
181 TARGET_BUILTIN(__builtin_ia32_phaddsw, "V4sV4sV4s", "", "ssse3")
182 TARGET_BUILTIN(__builtin_ia32_phaddw, "V4sV4sV4s", "", "ssse3")
183 TARGET_BUILTIN(__builtin_ia32_phsubd, "V2iV2iV2i", "", "ssse3")
184 TARGET_BUILTIN(__builtin_ia32_phsubsw, "V4sV4sV4s", "", "ssse3")
185 TARGET_BUILTIN(__builtin_ia32_phsubw, "V4sV4sV4s", "", "ssse3")
[all …]
/external/valgrind/none/tests/x86/
Dssse3_misaligned.vgtest2 prereq: test -x ssse3_misaligned && ../../../tests/x86_amd64_features x86-ssse3

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