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Searched refs:ssubw (Results 1 – 22 of 22) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s333 ssubw v0.8h, v1.8h, v2.8b
334 ssubw v0.4s, v1.4s, v2.4h
335 ssubw v0.2d, v1.2d, v2.2s
Dneon-diagnostics.s2703 ssubw v0.8h, v1.8h, v2.8h
2704 ssubw v0.4s, v1.4s, v2.4s
2705 ssubw v0.2d, v1.2d, v2.2d
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s674 ssubw v22.4s, v22.4s, v15.4h
683 ssubw v28.4s, v28.4s, v11.4h
687 ssubw v22.4s, v22.4s, v21.4h
696 ssubw v28.4s, v28.4s, v18.4h
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s509 ssubw v4.8h, v6.8h , v7.8b
563 ssubw v14.8h, v14.8h , v7.8b
Dihevc_deblk_luma_vert.s588 ssubw v2.8h, v2.8h , v20.8b
/external/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll283 ;CHECK: ssubw.8h
293 ;CHECK: ssubw.4s
303 ;CHECK: ssubw.2d
Darm64-neon-3vdiff.ll433 ; CHECK: ssubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
442 ; CHECK: ssubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
451 ; CHECK: ssubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1398 # CHECK: ssubw v0.8h, v1.8h, v2.8b
1399 # CHECK: ssubw v0.4s, v1.4s, v2.4h
1400 # CHECK: ssubw v0.2d, v1.2d, v2.2s
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1554 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s
1555 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h
1556 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b
Dlog-disasm1554 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s
1555 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h
1556 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b
Dlog-all3931 0x~~~~~~~~~~~~~~~~ 0eba32f9 ssubw v25.2d, v23.2d, v26.2s
3933 0x~~~~~~~~~~~~~~~~ 0e783255 ssubw v21.4s, v18.4s, v24.4h
3935 0x~~~~~~~~~~~~~~~~ 0e2332de ssubw v30.8h, v22.8h, v3.8b
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1788 __ ssubw(v25.V2D(), v23.V2D(), v26.V2S()); in GenerateTestSequenceNEON() local
1789 __ ssubw(v21.V4S(), v18.V4S(), v24.V4H()); in GenerateTestSequenceNEON() local
1790 __ ssubw(v30.V8H(), v22.V8H(), v3.V8B()); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4191 DEFINE_TEST_NEON_3DIFF_WIDE(ssubw, Basic)
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2396 LogicVRegister ssubw(VectorFormat vform,
Dassembler-aarch64.h2205 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
Dmacro-assembler-aarch64.h2206 V(ssubw, Ssubw) \
Dsimulator-aarch64.cc3646 ssubw(vf_l, rd, rn, rm); in VisitNEON3Different()
Dlogic-aarch64.cc3005 LogicVRegister Simulator::ssubw(VectorFormat vform, in ssubw() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc2016 void Assembler::ssubw(const VRegister& vd, in ssubw() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3755 void ssubw(const VRegister& vd,
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27435 ssubw v5.8h, v13.8h, v31.8b 61fa2da99ceb195cb6c3d92cc673cf9c 7cc351a5a62264bc6aa5b4e3cfd64d61 …
27437 ssubw v5.4s, v13.4s, v31.4h 4a1494510403422d9cbc639d09aec5de e72935cc478bbd1701ea2f6f17ee2276 …
27439 ssubw v5.2d, v13.2d, v31.2s 5f495e87024af059299b8e24b791c21b 9235e7be120edf891a13a12e195003c4 …
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3559 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",