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Searched refs:stw (Results 1 – 25 of 154) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dppc32-vaarg.ll20 ; CHECK-NEXT: stw 3, -4(1)
21 ; CHECK-NEXT: stw 6, -8(1)
22 ; CHECK-NEXT: stw 4, -12(1)
23 ; CHECK-NEXT: stw 5, -16(1)
27 ; CHECK-NEXT: stw 3, -8(1)
39 ; CHECK-NEXT: stw 0, -20(1)
40 ; CHECK-NEXT: stw 5, -24(1)
41 ; CHECK-NEXT: stw 3, -28(1)
42 ; CHECK-NEXT: stw 7, -32(1)
43 ; CHECK-NEXT: stw 8, -36(1)
[all …]
/external/valgrind/coregrind/m_dispatch/
Ddispatch-ppc32-linux.S74 stw 6,4(1)
108 stw 31,348(1)
109 stw 30,344(1)
110 stw 29,340(1)
111 stw 28,336(1)
112 stw 27,332(1)
113 stw 26,328(1)
114 stw 25,324(1)
115 stw 24,320(1)
116 stw 23,316(1)
[all …]
/external/libunwind_llvm/src/
DUnwindRegistersSave.S99 stw r0, 8(r3)
101 stw r0, 0(r3) ; store lr as ssr0
102 stw r1, 12(r3)
103 stw r2, 16(r3)
104 stw r3, 20(r3)
105 stw r4, 24(r3)
106 stw r5, 28(r3)
107 stw r6, 32(r3)
108 stw r7, 36(r3)
109 stw r8, 40(r3)
[all …]
/external/llvm/test/CodeGen/XCore/
Dllvm-intrinsics.ll33 ; CHECK: stw lr, sp[0]
107 ; CHECK: stw r4, sp[4]
109 ; CHECK: stw r5, sp[3]
158 ; CHECKFP: stw r10, sp[1]
160 ; CHECKFP: stw r4, r10[9]
161 ; CHECKFP: stw r5, r10[8]
162 ; CHECKFP: stw r6, r10[7]
163 ; CHECKFP: stw r7, r10[6]
164 ; CHECKFP: stw r8, r10[5]
165 ; CHECKFP: stw r9, r10[4]
[all …]
Dvarargs.ll7 ; CHECK: stw r[[REG:[0-3]{1,1}]]
9 ; CHECK: stw r[[REG:[0-3]{1,1}]]
11 ; CHECK: stw r[[REG:[0-3]{1,1}]]
13 ; CHECK: stw r[[REG:[0-3]{1,1}]]
28 ; CHECK: stw lr, sp[1]
29 ; CHECK: stw r0, sp[3]
30 ; CHECK: stw r1, sp[4]
31 ; CHECK: stw r2, sp[5]
32 ; CHECK: stw r3, sp[6]
34 ; CHECK: stw r0, sp[2]
[all …]
Dbigstructret.ll27 ; CHECK-NEXT: stw [[REGISTER]], sp[2]
41 ; CHECK: stw [[REGISTER]], sp[1]
65 ; CHECK: stw r1, r0[4]
67 ; CHECK: stw r1, r0[3]
69 ; CHECK: stw r1, r0[2]
71 ; CHECK: stw r1, r0[1]
73 ; CHECK: stw r1, r0[0]
DbyVal.ll17 ; CHECK: stw r4, sp[12]
18 ; CHECK: stw r5, sp[11]
40 ; CHECK: stw lr, sp[1]
41 ; CHECK: stw r2, sp[3]
42 ; CHECK: stw r3, sp[4]
44 ; CHECK: stw r0, sp[2]
Depilogue_prologue.ll11 ; CHECKFP-NEXT: stw r10, sp[1]
19 ; CHECK: stw lr, sp[0]
32 ; CHECKFP-NEXT: stw r10, sp[1]
34 ; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[2]
48 ; CHECK-NEXT: stw [[REG:r[4-9]+]], sp[1]
72 ; CHECKFP-NEXT: stw r10, sp[1]
125 ; CHECKFP-NEXT: stw r10, sp[1]
132 ; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
180 ; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
212 ; CHECKFP-NEXT: stw r10, sp[1]
[all …]
Dscavenging.ll77 ; CHECK: stw r4, sp[1]
83 ; CHECK: stw r5, sp[0]
86 ; CHECK: stw r0, r4[r5]
89 ; CHECK: stw r1, r0[r5]
92 ; CHECK: stw r2, r0[r1]
95 ; CHECK: stw r3, r0[r1]
98 ; CHECK: stw r11, r0[r1]
/external/llvm/test/CodeGen/PowerPC/
Dtls_get_addr_clobbers.ll27 ; CHECK-DAG: stw 3, 0([[BACKUP_3]])
28 ; CHECK-DAG: stw 3, 0([[BACKUP_4]])
29 ; CHECK-DAG: stw 3, 0([[BACKUP_5]])
30 ; CHECK-DAG: stw 3, 0([[BACKUP_6]])
31 ; CHECK-DAG: stw 3, 0([[BACKUP_7]])
32 ; CHECK-DAG: stw 3, 0([[BACKUP_8]])
33 ; CHECK-DAG: stw 3, 0([[BACKUP_9]])
34 ; CHECK-DAG: stw 3, 0([[BACKUP_10]])
Di32-to-float.ll22 ; CHECK-PWR6: stw 3,
29 ; CHECK-A2: stw 3,
35 ; CHECK-VSX: stw 3,
54 ; CHECK-PWR6: stw 3,
60 ; CHECK-A2: stw 3,
66 ; CHECK-VSX: stw 3,
78 ; CHECK-A2: stw 3,
84 ; CHECK-VSX: stw 3,
96 ; CHECK-A2: stw 3,
102 ; CHECK-VSX: stw 3,
Dcrsave.ll17 ; PPC32: stw 31, -4(1)
20 ; PPC32-NEXT: stw 12, 24(31)
26 ; PPC64: stw 12, 8(1)
46 ; PPC32: stw 31, -4(1)
49 ; PPC32-NEXT: stw 12, 24(31)
56 ; PPC64: stw 12, 8(1)
Dstfiwx.ll12 ; CHECK-NOT: stw
17 ; CHECK-LS: stw
34 ; CHECK-NOT: stw
39 ; CHECK-LS: stw
Dppc32-vacopy.ll22 ; CHECK: stw [[REG1]], {{.*}}
23 ; CHECK: stw [[REG2]], {{.*}}
24 ; CHECK: stw [[REG3]], {{.*}}
Dcc.ll24 ; CHECK-DAG: stw [[REG1]], 8(1)
25 ; CHECK-DAG: stw [[REG2]], -4(1)
57 ; CHECK-DAG: stw [[REG1]], 8(1)
58 ; CHECK-DAG: stw [[REG2]], -4(1)
Dstack-realign.ll82 ; CHECK-32-DAG: stw 30, -8(1)
84 ; CHECK-32-DAG: stw 0, 4(1)
91 ; CHECK-32-PIC-DAG: stw 29, -12(1)
93 ; CHECK-32-PIC-DAG: stw 0, 4(1)
135 ; CHECK-32-DAG: stw 30, -8(1)
137 ; CHECK-32-DAG: stw 0, 4(1)
149 ; CHECK-32-PIC-DAG: stw 29, -12(1)
151 ; CHECK-32-PIC-DAG: stw 0, 4(1)
Danon_aggr.ll35 ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
36 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
78 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
79 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
123 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
124 ; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]
168 ; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
169 ; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
/external/valgrind/coregrind/m_syswrap/
Dsyscall-ppc32-linux.S81 stw 31,28(1)
82 stw 30,24(1)
83 stw 29,20(1)
84 stw 28,16(1)
111 3: stw 3,OFFSET_ppc32_GPR3(30) /* gst->GPR3 = sc result */
/external/swiftshader/third_party/LLVM/test/CodeGen/XCore/
D2011-08-01-VarargsBug.ll6 ; CHECK: stw r[[REG:[0-3]{1,1}]]
8 ; CHECK: stw r[[REG:[0-3]{1,1}]]
10 ; CHECK: stw r[[REG:[0-3]{1,1}]]
12 ; CHECK: stw r[[REG:[0-3]{1,1}]]
Dbigstructret.ll34 ; CHECK: stw r1, r0[4]
36 ; CHECK: stw r1, r0[3]
38 ; CHECK: stw r1, r0[2]
40 ; CHECK: stw r1, r0[1]
42 ; CHECK: stw r1, r0[0]
/external/llvm/test/MC/Disassembler/XCore/
Dxcore.txt62 # CHECK: stw et, sp[4]
65 # CHECK: stw sed, sp[3]
68 # CHECK: stw spc, sp[1]
71 # CHECK: stw ssr, sp[2]
359 # CHECK: stw r3, r2[0]
406 # CHECK: stw r7, r10[r1]
533 # CHECK: stw r8, dp[14]
536 # CHECK: stw r9, dp[654]
539 # CHECK: stw lr, dp[23]
542 # CHECK: stw sp, dp[44442]
[all …]
/external/llvm/test/CodeGen/BPF/
Dcc_args.ll60 ; CHECK: stw 0(r2), r1
61 ; CHECK: stw 4(r2), r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
68 ; CHECK: stw 0(r3), r1
70 ; CHECK: stw 0(r3), r2
79 ; CHECK: stw 0(r1), r2
Dcc_args_be.ll61 ; CHECK: stw 4(r2), r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
62 ; CHECK: stw 0(r2), r1
69 ; CHECK: stw 0(r3), r1
71 ; CHECK: stw 0(r3), r2
80 ; CHECK: stw 0(r1), r2
/external/valgrind/VEX/orig_ppc32/
Dreturn0.orig19 0x254804E0: 90810000 stw r4,0(r1)
59 0x25471A74: 92E1028C stw r23,652(r1)
66 0x25471A78: 900102B4 stw r0,692(r1)
78 0x25471A80: 93010290 stw r24,656(r1)
90 0x25471A88: 93210294 stw r25,660(r1)
103 0x25471A90: 93410298 stw r26,664(r1)
110 0x25471A94: 9361029C stw r27,668(r1)
117 0x25471A98: 938102A0 stw r28,672(r1)
124 0x25471A9C: 93A102A4 stw r29,676(r1)
131 0x25471AA0: 93C102A8 stw r30,680(r1)
[all …]
Ddate.orig19 0x254804E0: 90810000 stw r4,0(r1)
59 0x25471A74: 92E1028C stw r23,652(r1)
66 0x25471A78: 900102B4 stw r0,692(r1)
78 0x25471A80: 93010290 stw r24,656(r1)
90 0x25471A88: 93210294 stw r25,660(r1)
103 0x25471A90: 93410298 stw r26,664(r1)
110 0x25471A94: 9361029C stw r27,668(r1)
117 0x25471A98: 938102A0 stw r28,672(r1)
124 0x25471A9C: 93A102A4 stw r29,676(r1)
131 0x25471AA0: 93C102A8 stw r30,680(r1)
[all …]

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