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/external/valgrind/none/tests/mips32/
Dmips32_dsp.c563 TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xfff45fff, t0, t8); in main()
571 TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xc4dbfe20, t0, t8); in main()
579 TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x8f8f8f80, t0, t8); in main()
587 TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xbc80f924, t0, t8); in main()
595 TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x73f39fca, t0, t8); in main()
609 TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xfff45fff, t0, t8); in main()
617 TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xc4dbfe20, t0, t8); in main()
625 TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x8f8f8f80, t0, t8); in main()
633 TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xbc80f924, t0, t8); in main()
641 TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x73f39fca, t0, t8); in main()
[all …]
Dmips32_dspr2.c556 TESTDSPINST_RD_RT_DSPC("absq_s.qb $t0, $t8", 0xfff45fff, t0, t8); in main()
564 TESTDSPINST_RD_RT_DSPC("absq_s.qb $t0, $t8", 0xc4dbfe20, t0, t8); in main()
572 TESTDSPINST_RD_RT_DSPC("absq_s.qb $t0, $t8", 0x8f8f8f80, t0, t8); in main()
580 TESTDSPINST_RD_RT_DSPC("absq_s.qb $t0, $t8", 0xbc80f924, t0, t8); in main()
588 TESTDSPINST_RD_RT_DSPC("absq_s.qb $t0, $t8", 0x73f39fca, t0, t8); in main()
603 t2, t4, t8); in main()
605 t0, t8, t0); in main()
617 t2, t4, t8); in main()
619 t0, t8, t0); in main()
633 t2, t4, t8); in main()
[all …]
Dbranches.c269 TESTINST1(22, t8); in main()
295 TESTINST2(22, t8); in main()
321 TESTINST3(22, t8); in main()
339 TESTINST4("beq", 14, -1, 0x5, v0, t9, t8); in main()
340 TESTINST4("beq", 15, -1, -1, t9, t8, a3); in main()
357 TESTINST4("bne", 14, -1, 0x5, v0, t9, t8); in main()
358 TESTINST4("bne", 15, -1, -1, t9, t8, a3); in main()
376 TESTINST5("beqz", 15, -1, t9, t8); in main()
394 TESTINST5("bgez", 15, -1, t9, t8); in main()
412 TESTINST5("bgtz", 15, -1, t9, t8); in main()
[all …]
Dmips32_dsp.stdout.exp-LE8 absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0
16 absq_s.ph $t0, $t8 :: rd 0x3b2501e0 rt 0xc4dbfe20 DSPControl 0x0
24 absq_s.ph $t0, $t8 :: rd 0x70717080 rt 0x8f8f8f80 DSPControl 0x0
32 absq_s.ph $t0, $t8 :: rd 0x438006dc rt 0xbc80f924 DSPControl 0x0
40 absq_s.ph $t0, $t8 :: rd 0x73f36036 rt 0x73f39fca DSPControl 0x0
53 absq_s.w $t0, $t8 :: rd 0x000ba001 rt 0xfff45fff DSPControl 0x0
61 absq_s.w $t0, $t8 :: rd 0x3b2401e0 rt 0xc4dbfe20 DSPControl 0x0
69 absq_s.w $t0, $t8 :: rd 0x70707080 rt 0x8f8f8f80 DSPControl 0x0
77 absq_s.w $t0, $t8 :: rd 0x437f06dc rt 0xbc80f924 DSPControl 0x0
85 absq_s.w $t0, $t8 :: rd 0x73f39fca rt 0x73f39fca DSPControl 0x0
[all …]
Dmips32_dsp.stdout.exp-BE8 absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0
16 absq_s.ph $t0, $t8 :: rd 0x3b2501e0 rt 0xc4dbfe20 DSPControl 0x0
24 absq_s.ph $t0, $t8 :: rd 0x70717080 rt 0x8f8f8f80 DSPControl 0x0
32 absq_s.ph $t0, $t8 :: rd 0x438006dc rt 0xbc80f924 DSPControl 0x0
40 absq_s.ph $t0, $t8 :: rd 0x73f36036 rt 0x73f39fca DSPControl 0x0
53 absq_s.w $t0, $t8 :: rd 0x000ba001 rt 0xfff45fff DSPControl 0x0
61 absq_s.w $t0, $t8 :: rd 0x3b2401e0 rt 0xc4dbfe20 DSPControl 0x0
69 absq_s.w $t0, $t8 :: rd 0x70707080 rt 0x8f8f8f80 DSPControl 0x0
77 absq_s.w $t0, $t8 :: rd 0x437f06dc rt 0xbc80f924 DSPControl 0x0
85 absq_s.w $t0, $t8 :: rd 0x73f39fca rt 0x73f39fca DSPControl 0x0
[all …]
/external/libjpeg-turbo/simd/
Djsimd_mips_dspr2.S71 addu t8, t7, s0
72 addu t2, t8, s0
75 lbu t8, 0(t8)
81 sb t8, -1(t5)
107 addu t8, t7, s0
108 addu t2, t8, s0
111 lbu t8, 0(t8)
117 sb t8, -1(t5)
176 li t8, 0x807fff // CBCR_OFFSET + ONE_HALF-1
196 mtlo t8, $ac1
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dvec_ins_extract-1.ll6 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
7 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
11 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
12 %t13 = insertelement <4 x i32> %t8, i32 76, i32 0
16 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
17 %t9 = extractelement <4 x i32> %t8, i32 %t7
18 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
21 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
22 %t9 = extractelement <4 x i32> %t8, i32 0
23 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
Dmasked-iv-unsafe.ll27 %t8 = fmul double %t7, 4.5
28 store double %t8, double* %t6
55 %t8 = fmul double %t7, 4.5
56 store double %t8, double* %t6
85 %t8 = fmul double %t7, 4.5
86 store double %t8, double* %t6
115 %t8 = fmul double %t7, 4.5
116 store double %t8, double* %t6
143 %t8 = fmul double %t7, 4.5
144 store double %t8, double* %t6
[all …]
Dmasked-iv-safe.ll32 %t8 = fmul double %t7, 4.5
33 store double %t8, double* %t6
60 %t8 = fmul double %t7, 4.5
61 store double %t8, double* %t6
90 %t8 = fmul double %t7, 4.5
91 store double %t8, double* %t6
120 %t8 = fmul double %t7, 4.5
121 store double %t8, double* %t6
148 %t8 = fmul double %t7, 4.5
149 store double %t8, double* %t6
[all …]
/external/valgrind/VEX/orig_ppc32/
Ddate.orig21 11: GETL R1, t8
22 12: STL t6, (t8)
55 12: GETL R11, t8
56 13: PUTL t8, CTR
253 8: LDL (t6), t8
254 9: PUTL t8, R8
366 12: MOVL $0x6FFF0000, t8
367 13: PUTL t8, R29
444 9: LDL (t6), t8
445 10: PUTL t8, R11
[all …]
Dreturn0.orig21 11: GETL R1, t8
22 12: STL t6, (t8)
55 12: GETL R11, t8
56 13: PUTL t8, CTR
253 8: LDL (t6), t8
254 9: PUTL t8, R8
366 12: MOVL $0x6FFF0000, t8
367 13: PUTL t8, R29
444 9: LDL (t6), t8
445 10: PUTL t8, R11
[all …]
/external/llvm/test/CodeGen/X86/
Dmasked-iv-unsafe.ll27 %t8 = fmul double %t7, 4.5
28 store double %t8, double* %t6
55 %t8 = fmul double %t7, 4.5
56 store double %t8, double* %t6
85 %t8 = fmul double %t7, 4.5
86 store double %t8, double* %t6
115 %t8 = fmul double %t7, 4.5
116 store double %t8, double* %t6
143 %t8 = fmul double %t7, 4.5
144 store double %t8, double* %t6
[all …]
Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
29 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
34 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
57 %t13 = insertelement <4 x i32> %t8, i32 76, i32 0
62 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
81 %t9 = extractelement <4 x i32> %t8, i32 %t7
82 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
86 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
107 %t9 = extractelement <4 x i32> %t8, i32 0
108 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
Dmasked-iv-safe.ll29 %t8 = fmul double %t7, 4.5
30 store double %t8, double* %t6
62 %t8 = fmul double %t7, 4.5
63 store double %t8, double* %t6
97 %t8 = fmul double %t7, 4.5
98 store double %t8, double* %t6
132 %t8 = fmul double %t7, 4.5
133 store double %t8, double* %t6
165 %t8 = fmul double %t7, 4.5
166 store double %t8, double* %t6
[all …]
/external/libvorbis/lib/
Dsmallft.c276 int t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10; in dradfg() local
446 t8=t4; in dradfg()
449 ch2[t6++]+=ar2*c2[t8++]; in dradfg()
525 t8=t4; in dradfg()
530 cc[i+t7-1]=ch[i+t8-1]+ch[i+t9-1]; in dradfg()
531 cc[ic+t6-1]=ch[i+t8-1]-ch[i+t9-1]; in dradfg()
532 cc[i+t7]=ch[i+t8]+ch[i+t9]; in dradfg()
533 cc[ic+t6]=ch[i+t9]-ch[i+t8]; in dradfg()
537 t8+=ido; in dradfg()
557 t8=i+t4; in dradfg()
[all …]
/external/speex/libspeex/
Dsmallft.c278 int t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10; in dradfg() local
448 t8=t4; in dradfg()
451 ch2[t6++]+=ar2*c2[t8++]; in dradfg()
527 t8=t4; in dradfg()
532 cc[i+t7-1]=ch[i+t8-1]+ch[i+t9-1]; in dradfg()
533 cc[ic+t6-1]=ch[i+t8-1]-ch[i+t9-1]; in dradfg()
534 cc[i+t7]=ch[i+t8]+ch[i+t9]; in dradfg()
535 cc[ic+t6]=ch[i+t9]-ch[i+t8]; in dradfg()
539 t8+=ido; in dradfg()
559 t8=i+t4; in dradfg()
[all …]
/external/ltp/runtest/
Dltp-aio-stress.part140 ADS1011 aio-stress -I500 -o3 -S -r256 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file3 $TMPDIR/…
41 ADS1012 aio-stress -I500 -o3 -S -r512 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file3 $TMPDIR/f…
42 ADS1013 aio-stress -I500 -o2 -O -r4 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file3 $TMPDIR/…
53 ADS1024 aio-stress -I500 -o3 -O -r256 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TMPDIR…
54 ADS1025 aio-stress -I500 -o3 -O -r512 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TMPDIR/…
55 ADS1026 aio-stress -I500 -o0 -S -r4 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $T…
66 ADS1037 aio-stress -I500 -o1 -S -r256 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TMP…
67 ADS1038 aio-stress -I500 -o1 -S -r512 -t8 -x $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TMP…
68 ADS1039 aio-stress -I500 -o1 -O -r4 -t8 -x $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file…
76 ADS1047 aio-stress -I500 -o1 -O -r32 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TM…
[all …]
/external/v8/src/mips/
Dmacro-assembler-mips.cc204 DCHECK(!AreAliased(value, dst, t8, object)); in RecordWriteField()
221 And(t8, dst, Operand((1 << kPointerSizeLog2) - 1)); in RecordWriteField()
222 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
333 DCHECK(!AreAliased(object, address, value, t8)); in RecordWrite()
472 li(t8, Operand(store_buffer)); in RememberedSetHelper()
473 lw(scratch, MemOperand(t8)); in RememberedSetHelper()
478 sw(scratch, MemOperand(t8)); in RememberedSetHelper()
481 And(t8, scratch, Operand(StoreBuffer::kStoreBufferMask)); in RememberedSetHelper()
483 Branch(&done, ne, t8, Operand(zero_reg)); in RememberedSetHelper()
486 Ret(ne, t8, Operand(zero_reg)); in RememberedSetHelper()
[all …]
Dcodegen-mips.cc77 __ xor_(t8, a1, a0); in CreateMemCopyUint8Function()
78 __ andi(t8, t8, loadstore_chunk - 1); // t8 is a0/a1 word-displacement. in CreateMemCopyUint8Function()
79 __ bne(t8, zero_reg, &unaligned); in CreateMemCopyUint8Function()
87 __ lwr(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
89 __ swr(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
92 __ lwl(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
94 __ swl(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
102 __ andi(t8, a2, 0x3f); in CreateMemCopyUint8Function()
103 __ beq(a2, t8, &chkw); // Less than 64? in CreateMemCopyUint8Function()
104 __ subu(a3, a2, t8); // In delay slot. in CreateMemCopyUint8Function()
[all …]
/external/v8/src/mips64/
Dcodegen-mips64.cc77 __ xor_(t8, a1, a0); in CreateMemCopyUint8Function()
78 __ andi(t8, t8, loadstore_chunk - 1); // t8 is a0/a1 word-displacement. in CreateMemCopyUint8Function()
79 __ bne(t8, zero_reg, &unaligned); in CreateMemCopyUint8Function()
87 __ lwr(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
89 __ swr(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
92 __ lwl(t8, MemOperand(a1)); in CreateMemCopyUint8Function()
94 __ swl(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
103 __ andi(t8, a2, 0x3f); in CreateMemCopyUint8Function()
104 __ beq(a2, t8, &chkw); // Less than 64? in CreateMemCopyUint8Function()
105 __ subu(a3, a2, t8); // In delay slot. in CreateMemCopyUint8Function()
[all …]
Dmacro-assembler-mips64.cc220 DCHECK(!AreAliased(value, dst, t8, object)); in RecordWriteField()
237 And(t8, dst, Operand((1 << kPointerSizeLog2) - 1)); in RecordWriteField()
238 Branch(&ok, eq, t8, Operand(zero_reg)); in RecordWriteField()
349 DCHECK(!AreAliased(object, address, value, t8)); in RecordWrite()
488 li(t8, Operand(store_buffer)); in RememberedSetHelper()
489 ld(scratch, MemOperand(t8)); in RememberedSetHelper()
494 sd(scratch, MemOperand(t8)); in RememberedSetHelper()
497 And(t8, scratch, Operand(StoreBuffer::kStoreBufferMask)); in RememberedSetHelper()
498 DCHECK(!scratch.is(t8)); in RememberedSetHelper()
500 Branch(&done, ne, t8, Operand(zero_reg)); in RememberedSetHelper()
[all …]
/external/llvm/test/CodeGen/Mips/
Dllcarry.ll18 ; 16: move ${{[0-9]+}}, $t8
31 ; 16: move ${{[0-9]+}}, $t8
44 ; 16: move ${{[0-9]+}}, $t8
/external/compiler-rt/test/asan/TestCases/Posix/
Dstack-overflow.cc37 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13; in recursive_func()
46 t8 = z8; in recursive_func()
61 z8 = t8; in recursive_func()
/external/llvm/test/Transforms/Reassociate/
Dmightymul.ll13 %t8 = mul i32 %t7, %t7
14 %t9 = mul i32 %t8, %t8
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dlshr-phi.ll17 %k.04 = phi i32 [ 0, %entry ], [ %t8, %bb ] ; <i32> [#uses=2]
25 %t8 = and i32 %t7, 16383 ; <i32> [#uses=2]
33 %k.0.lcssa = phi i32 [ 0, %entry ], [ %t8, %bb ] ; <i32> [#uses=1]

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