Searched +refs:tablegen +refs:mode (Results 1 – 25 of 86) sorted by relevance
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/external/swiftshader/third_party/LLVM/utils/emacs/ |
D | README | 6 * llvm-mode.el 8 Syntax highlighting mode for LLVM assembly files. To use, add this code to 13 (require 'llvm-mode) 15 * tablegen-mode.el 17 Syntax highlighting mode for TableGen description files. To use, add this code 22 (require 'tablegen-mode)
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/external/llvm/utils/emacs/ |
D | README | 6 * llvm-mode.el 8 Syntax highlighting mode for LLVM assembly files. To use, add this code to 13 (require 'llvm-mode) 15 * tablegen-mode.el 17 Syntax highlighting mode for TableGen description files. To use, add this code 22 (require 'tablegen-mode)
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/external/swiftshader/third_party/LLVM/utils/vim/ |
D | README | 7 Syntax highlighting mode for LLVM assembly files. To use, copy `llvm.vim' to 14 * tablegen.vim 16 Syntax highlighting mode for TableGen description files. To use, copy 17 `tablegen.vim' to ~/.vim/syntax and add this code to your ~/.vimrc : 20 au! BufRead,BufNewFile *.td set filetype=tablegen 40 " LLVM Makefile highlighting mode
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D | vimrc | 82 " Enable syntax highlighting for tablegen files. To use, copy 83 " utils/vim/tablegen.vim to ~/.vim/syntax . 85 au! BufRead,BufNewFile *.td set filetype=tablegen 109 " In findstart mode, look for the beginning of the current identifier.
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/external/swiftshader/third_party/LLVM/utils/jedit/ |
D | README | 5 * tablegen.xml 7 Syntax highlighting mode for TableGen description files. To use, copy this 10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
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/external/llvm/utils/jedit/ |
D | README | 5 * tablegen.xml 7 Syntax highlighting mode for TableGen description files. To use, copy this 10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
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/external/llvm/utils/vim/ |
D | README | 4 tablegen *.td files. It comes with filetype detection rules in the (ftdetect), 19 " LLVM Makefile highlighting mode
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D | vimrc | 82 " Enable syntax highlighting for tablegen files. To use, copy 83 " utils/vim/tablegen.vim to ~/.vim/syntax . 85 au! BufRead,BufNewFile *.td set filetype=tablegen 116 " In findstart mode, look for the beginning of the current identifier.
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | Sparc.td | 1 //===- Sparc.td - Describe the Sparc Target Machine --------*- tablegen -*-===// 28 "Enable deprecated V8 instructions in V9 mode">;
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/external/llvm/lib/Target/Sparc/ |
D | LeonFeatures.td | 1 //===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===// 67 "LEON3 erratum fix: Prevent any rounding mode change " 68 "request: use only the round-to-nearest rounding mode">;
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D | Sparc.td | 1 //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// 27 "Enable deprecated V8 instructions in V9 mode">;
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILBase.td | 1 //===- AMDIL.td - AMDIL Target Machine -------------*- tablegen -*-===// 66 "Debug mode is enabled, so disable hardware accelerated address spaces.">;
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D | AMDILInstrInfo.td | 1 //===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===// 154 // Complex addressing mode patterns
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARM.td | 1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===// 23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24 "Thumb mode">; 26 def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", 27 "Native client mode">; 44 "Does not support ARM mode execution">;
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D | ARMScheduleV6.td | 1 //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// 192 // RunFast mode so that NFP pipeline is used for single-precision when
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/external/llvm/lib/Target/Mips/ |
D | MipsCallingConv.td | 1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 65 // tablegen-erated code. 102 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or 103 // in D0 and D1 in FP32bit mode. 189 // whether the result was originally an f128 into the tablegen-erated code. 326 // whether the argument was originally an f128 into the tablegen-erated code.
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D | Mips.td | 1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 33 // Predicate for marking the instruction as usable in hard-float mode only. 157 "Mips16 mode">; 171 "microMips mode">;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86.td | 1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// 23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 24 "64-bit mode (x86_64)">; 26 def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", 27 "Native Client mode">; 70 // without disabling 64-bit mode.
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrControl.td | 1 //===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*- 42 // jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsCallingConv.td | 1 //===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===// 93 // Single fp arguments are passed in pairs within 32-bit mode
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D | MipsInstrFPU.td | 1 //===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===// 18 // - 32 64-bit registers (default mode) 19 // - 16 even 32-bit registers (32-bit compatible mode) for 23 // - 32 32-bit registers (within single-only mode) 68 // single precision in 32 32bit fp registers in SingleOnly mode
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D | MipsRegisterInfo.td | 1 //===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// 194 /// Mips Double point precision FPU Registers in MFP64 mode. 276 // * FGR32 - 32 32-bit registers (single float only mode)
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/external/llvm/lib/Target/ARM/ |
D | ARMScheduleV6.td | 1 //===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===// 192 // RunFast mode so that NFP pipeline is used for single-precision when
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrFormats.td | 1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 45 def NoAddrMode : AddrModeType<0>; // No addressing mode 46 def Absolute : AddrModeType<1>; // Absolute addressing mode 47 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode 51 def PostInc : AddrModeType<6>; // Post increment addressing mode 160 // Addressing mode for load/store instructions.
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/external/llvm/lib/Target/AVR/ |
D | AVRInstrFormats.td | 1 //===-- AVRInstrInfo.td - AVR Instruction Formats ----------*- tablegen -*-===// 190 class FSTLD<bit type, bits<2> mode, dag outs, dag ins, 198 // This bit varies depending on the arguments and the mode. 209 let Inst{1-0} = mode{1-0};
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