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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dlea-recursion.ll17 %tmp8 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#uses=1]
19 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=2]
21 %tmp8.1 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#uses=1]
23 %tmp10.1 = add i32 %tmp9.1, %tmp8.1 ; <i32> [#uses=2]
25 %tmp8.2 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 2) ; <i32> [#uses=1]
27 %tmp10.2 = add i32 %tmp9.2, %tmp8.2 ; <i32> [#uses=2]
29 %tmp8.3 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 3) ; <i32> [#uses=1]
31 %tmp10.3 = add i32 %tmp9.3, %tmp8.3 ; <i32> [#uses=2]
33 %tmp8.4 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 4) ; <i32> [#uses=1]
35 %tmp10.4 = add i32 %tmp9.4, %tmp8.4 ; <i32> [#uses=2]
[all …]
Dxor.ll49 %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
54 %tmp8 = shl i32 %tmp6, 1
55 %tmp10 = icmp eq i32 %tmp8, 0
72 %b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
77 %tmp8 = shl i16 %tmp6, 1
78 %tmp10 = icmp eq i16 %tmp8, 0
94 %b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
99 %tmp8 = shl i8 %tmp6, 1
100 %tmp10 = icmp eq i8 %tmp8, 0
116 %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
[all …]
Dvec_set-5.ll8 %tmp8 = insertelement <4 x float> %tmp6, float %b, i32 2 ; <<4 x float>> [#uses=1]
9 %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
16 %tmp8 = insertelement <4 x float> %tmp7, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
17 %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
24 %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2 ; <<4 x i32>> [#uses=1]
25 %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3 ; <<4 x i32>> [#uses=1]
Dcoalescer-commute2.ll15 %tmp8 = bitcast <2 x i64> %x to <8 x i16> ; <<8 x i16>> [#uses=1]
16 %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
24 %tmp8 = bitcast <2 x i64> %y to <8 x i16> ; <<8 x i16>> [#uses=1]
25 %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
34 %tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
36 %add = fadd <4 x float> %tmp8, %V
Dpr1462.ll10 %tmp8 = add i128 %b2, %a1 ; <i128> [#uses=3]
12 %tmp18 = icmp sgt i128 %tmp8, %a1 ; <i1> [#uses=1]
13 %tmp14 = icmp slt i128 %tmp8, %a1 ; <i1> [#uses=1]
22 ret i128 %tmp8
Dvec_set-F.ll9 %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
10 ret <2 x i64> %tmp8
15 %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
16 %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
Dvec_shuffle-35.ll12 …%tmp8 = shufflevector <16 x i8> %T0, <16 x i8> undef, <16 x i32> < i32 1, i32 0, i32 3, i32 2, i32…
13 ret <16 x i8> %tmp8
18 …%tmp8 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> < i32 undef, i32 undef, i32 3, i32 …
19 ret <16 x i8> %tmp8
/external/llvm/test/CodeGen/X86/
Dlea-recursion.ll17 …%tmp8 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#us…
19 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=2]
21 …%tmp8.1 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#…
23 %tmp10.1 = add i32 %tmp9.1, %tmp8.1 ; <i32> [#uses=2]
25 …%tmp8.2 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 2) ; <i32> [#…
27 %tmp10.2 = add i32 %tmp9.2, %tmp8.2 ; <i32> [#uses=2]
29 …%tmp8.3 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 3) ; <i32> [#…
31 %tmp10.3 = add i32 %tmp9.3, %tmp8.3 ; <i32> [#uses=2]
33 …%tmp8.4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 4) ; <i32> [#…
35 %tmp10.4 = add i32 %tmp9.4, %tmp8.4 ; <i32> [#uses=2]
[all …]
Dxor.ll49 %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
54 %tmp8 = shl i32 %tmp6, 1
55 %tmp10 = icmp eq i32 %tmp8, 0
72 %b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
77 %tmp8 = shl i16 %tmp6, 1
78 %tmp10 = icmp eq i16 %tmp8, 0
94 %b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
99 %tmp8 = shl i8 %tmp6, 1
100 %tmp10 = icmp eq i8 %tmp8, 0
116 %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
[all …]
Dpr1462.ll9 %tmp8 = add i128 %b2, %a1 ; <i128> [#uses=3]
11 %tmp18 = icmp sgt i128 %tmp8, %a1 ; <i1> [#uses=1]
12 %tmp14 = icmp slt i128 %tmp8, %a1 ; <i1> [#uses=1]
21 ret i128 %tmp8
Dvec_set-F.ll13 %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
14 ret <2 x i64> %tmp8
23 %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
24 %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
Dcoalescer-commute2.ll15 %tmp8 = bitcast <2 x i64> %x to <8 x i16> ; <<8 x i16>> [#uses=1]
16 %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
24 %tmp8 = bitcast <2 x i64> %y to <8 x i16> ; <<8 x i16>> [#uses=1]
25 %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
/external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dpitch_estimator_mips.c34 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
80 [tmp7] "=&r" (tmp7), [tmp8] "=&r" (tmp8), [tmp_in] "+r" (tmp_in), in WebRtcIsacfix_PCorr2Q32()
105 int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; in WebRtcIsacfix_PCorr2Q32() local
172 [tmp7] "=&r" (tmp7), [tmp8] "=&r" (tmp8), [inptr] "+r" (inptr), in WebRtcIsacfix_PCorr2Q32()
/external/llvm/test/Transforms/TailCallElim/
Ddont_reorder_load.ll23 …%tmp8 = call fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
25 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
42 …%tmp8 = call fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
44 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
60 …%tmp8 = call fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
62 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
78 …%tmp8 = call fastcc i32 @no_tailrecelim_4(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
80 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
Dreorder_load.ll31 %tmp8 = call fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
33 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
62 %tmp8 = call fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
64 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
86 %tmp8 = call fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
88 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
120 %tmp8 = call fastcc i32 @raise_load_4(i32* %a_arg, i32 %first, i32 %tmp7) ; <i32> [#uses=1]
122 %tmp10 = add i32 %second, %tmp8 ; <i32> [#uses=1]
143 %tmp8 = call fastcc i32 @raise_load_5(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
145 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
/external/llvm/test/Transforms/Reassociate/
Drepeats.ll120 %tmp8 = mul i4 %tmp7, %x
121 ret i4 %tmp8
138 %tmp8 = mul i4 %tmp7, %x
139 %tmp9 = mul i4 %tmp8, %x
158 %tmp8 = mul i4 %tmp7, %x
159 %tmp9 = mul i4 %tmp8, %x
177 %tmp8 = mul i4 %tmp7, %x
178 %tmp9 = mul i4 %tmp8, %x
198 %tmp8 = mul i4 %tmp7, %x
199 %tmp9 = mul i4 %tmp8, %x
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
D2006-01-20-ShiftPartsCrash.ll14 %tmp8 = ashr i64 %tmp7, %shift.upgrd.2 ; <i64> [#uses=1]
15 %tmp8.upgrd.3 = trunc i64 %tmp8 to i32 ; <i32> [#uses=1]
16 store i32 %tmp8.upgrd.3, i32* %b
D2006-09-28-shift_64.ll20 %tmp8 = and i32 %tmp7.upgrd.2, 1 ; <i32> [#uses=1]
21 %tmp8.upgrd.3 = icmp eq i32 %tmp8, 0 ; <i1> [#uses=1]
23 br i1 %tmp8.upgrd.3, label %cond_false, label %cond_true24
/external/llvm/test/CodeGen/PowerPC/
D2006-01-20-ShiftPartsCrash.ll15 %tmp8 = ashr i64 %tmp7, %shift.upgrd.2 ; <i64> [#uses=1]
16 %tmp8.upgrd.3 = trunc i64 %tmp8 to i32 ; <i32> [#uses=1]
17 store i32 %tmp8.upgrd.3, i32* %b
D2006-09-28-shift_64.ll20 %tmp8 = and i32 %tmp7.upgrd.2, 1 ; <i32> [#uses=1]
21 %tmp8.upgrd.3 = icmp eq i32 %tmp8, 0 ; <i1> [#uses=1]
23 br i1 %tmp8.upgrd.3, label %cond_false, label %cond_true24
/external/swiftshader/third_party/LLVM/test/Transforms/TailCallElim/
Dreorder_load.ll24 %tmp8 = call fastcc i32 @raise_load_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
26 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
50 %tmp8 = call fastcc i32 @raise_load_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
52 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
69 %tmp8 = call fastcc i32 @raise_load_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
71 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
97 %tmp8 = call fastcc i32 @raise_load_4(i32* %a_arg, i32 %first, i32 %tmp7) ; <i32> [#uses=1]
99 %tmp10 = add i32 %second, %tmp8 ; <i32> [#uses=1]
Ddont_reorder_load.ll23 …%tmp8 = call fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
25 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
42 …%tmp8 = call fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
44 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
60 …%tmp8 = call fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=…
62 %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dvecinsert.ll62 %tmp8 = insertelement <16 x i8> %tmp3, i8 2, i32 11
63 store <16 x i8> %tmp8, <16 x i8>* %arrayidx
72 %tmp8 = insertelement <8 x i16> %tmp3, i16 2, i32 6
73 store <8 x i16> %tmp8, <8 x i16>* %arrayidx
82 %tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
83 store <4 x i32> %tmp8, <4 x i32>* %arrayidx
92 %tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
93 store <4 x float> %tmp8, <4 x float>* %arrayidx
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Difcvt2.ll8 %tmp8 = or i1 %tmp5, %tmp2
10 br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
31 %tmp8 = and i1 %tmp5, %tmp2
33 br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
/external/llvm/test/CodeGen/ARM/
Difcvt2.ll8 %tmp8 = or i1 %tmp5, %tmp2
10 br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
31 %tmp8 = and i1 %tmp5, %tmp2
33 br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock

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