| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 388 uqrshrn2 v0.16b, v1.8h, #3
389 uqrshrn2 v0.8h, v1.4s, #3
390 uqrshrn2 v0.4s, v1.2d, #3
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| D | arm64-advsimd.s | 1570 uqrshrn2.16b v0, v0, #2
1572 uqrshrn2.8h v0, v0, #4
1574 uqrshrn2.4s v0, v0, #6
1742 ; CHECK: uqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x6f]
1744 ; CHECK: uqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x6f]
1746 ; CHECK: uqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x6f]
1841 uqrshrn2 v8.16b, v9.8h, #2
1843 uqrshrn2 v6.8h, v7.4s, #4
1845 uqrshrn2 v4.4s, v5.2d, #6
1906 ; CHECK: uqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x6f]
[all …]
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| D | neon-diagnostics.s | 2013 uqrshrn2 v0.16b, v1.8h, #17
2014 uqrshrn2 v0.8h, v1.4s, #33
2015 uqrshrn2 v0.4s, v1.2d, #65
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-shift.ll | 533 ; CHECK: uqrshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
544 ; CHECK: uqrshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
555 ; CHECK: uqrshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
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| D | arm64-vshift.ll | 1039 ;CHECK: uqrshrn2.16b v0, {{v[0-9]+}}, #1
1049 ;CHECK: uqrshrn2.8h v0, {{v[0-9]+}}, #1
1059 ;CHECK: uqrshrn2.4s v0, {{v[0-9]+}}, #1
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1069 # CHECK: uqrshrn2 v0.16b, v1.8h, #3
1070 # CHECK: uqrshrn2 v0.8h, v1.4s, #3
1071 # CHECK: uqrshrn2 v0.4s, v1.2d, #3
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| D | arm64-advsimd.txt | 2145 # CHECK: uqrshrn2.16b v0, v0, #0x6
2147 # CHECK: uqrshrn2.8h v0, v0, #0xc
2149 # CHECK: uqrshrn2.4s v0, v0, #0x1a
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28185 uqrshrn2 v4.4s, v29.2d, #1 1176b1373eb58df0ce7ef43a33a96d69 6210f7b4bbf439d2e6a403d90650459f f…
28186 uqrshrn2 v4.4s, v29.2d, #17 37c57938d5149b54dac8dd1134d93193 889755f485f82cee30373758a526535a …
28187 uqrshrn2 v4.4s, v29.2d, #32 41e8dd0bdaba3f2c3faab7ddd5d49f14 2aea283ed4bb0d37685b3405fe3f6324 …
28191 uqrshrn2 v4.8h, v29.4s, #1 c9470b09b3973194b9ad022a2a2d8109 02ba7e4bc6bb618e26137b0321be3b6d f…
28192 uqrshrn2 v4.8h, v29.4s, #9 e4b21e157abf65d071ac2de4933ee362 ac2e37e650588ad2ac2b02b6b945f7a7 f…
28193 uqrshrn2 v4.8h, v29.4s, #16 22330c33ef6f70bfc28489d3dd5a3052 12afa4cc9ff4e181611491d64a4ff530 …
28197 uqrshrn2 v4.16b, v29.8h, #1 7bb3e3c512d98ef68f61a121cd1406f6 1d3f64ee6d2f7b9d6ab1dc5a3d067b7b f…
28198 uqrshrn2 v4.16b, v29.8h, #4 2a95763cdc8f6de1d17ffa87deccf02f 91766313d0c8b5cdef76961693e26513 f…
28199 uqrshrn2 v4.16b, v29.8h, #8 d4c3fd3dac85bb7783ad9c9a27475cf8 99f22ef95018b5627c4470b83af929f3 9…
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| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 1986 0x~~~~~~~~~~~~~~~~ 6f0e9fd9 uqrshrn2 v25.16b, v30.8h, #2
1987 0x~~~~~~~~~~~~~~~~ 6f209dd5 uqrshrn2 v21.4s, v14.2d, #32
1988 0x~~~~~~~~~~~~~~~~ 6f1e9ced uqrshrn2 v13.8h, v7.4s, #2
|
| D | log-disasm | 1986 0x~~~~~~~~~~~~~~~~ 6f0e9fd9 uqrshrn2 v25.16b, v30.8h, #2
1987 0x~~~~~~~~~~~~~~~~ 6f209dd5 uqrshrn2 v21.4s, v14.2d, #32
1988 0x~~~~~~~~~~~~~~~~ 6f1e9ced uqrshrn2 v13.8h, v7.4s, #2
|
| D | log-all | 5275 0x~~~~~~~~~~~~~~~~ 6f0e9fd9 uqrshrn2 v25.16b, v30.8h, #2
5277 0x~~~~~~~~~~~~~~~~ 6f209dd5 uqrshrn2 v21.4s, v14.2d, #32
5279 0x~~~~~~~~~~~~~~~~ 6f1e9ced uqrshrn2 v13.8h, v7.4s, #2
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2329 __ uqrshrn2(v25.V16B(), v30.V8H(), 2); in GenerateTestSequenceNEON() local
2330 __ uqrshrn2(v21.V4S(), v14.V2D(), 32); in GenerateTestSequenceNEON() local
2331 __ uqrshrn2(v13.V8H(), v7.V4S(), 2); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2614 LogicVRegister uqrshrn2(VectorFormat vform,
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| D | assembler-aarch64.h | 2292 void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift);
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| D | macro-assembler-aarch64.h | 2430 V(uqrshrn2, Uqrshrn2) \
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| D | simulator-aarch64.cc | 5083 uqrshrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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| D | logic-aarch64.cc | 2739 LogicVRegister Simulator::uqrshrn2(VectorFormat vform, in uqrshrn2() function in vixl::aarch64::Simulator
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| D | assembler-aarch64.cc | 3845 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn2() function in vixl::aarch64::Assembler
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4384 void uqrshrn2(const VRegister& vd,
|