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Searched refs:ushl (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-shift.s28 ushl v0.8b, v1.8b, v2.8b
29 ushl v0.16b, v1.16b, v2.16b
30 ushl v0.4h, v1.4h, v2.4h
31 ushl v0.8h, v1.8h, v2.8h
32 ushl v0.2s, v1.2s, v2.2s
33 ushl v0.4s, v1.4s, v2.4s
34 ushl v0.2d, v1.2d, v2.2d
Dneon-scalar-shift.s13 ushl d17, d31, d8
Dneon-diagnostics.s916 ushl v1.16b, v25.16b, v6.8h
972 ushl b2, b0, b1
Darm64-advsimd.s370 ushl.8b v0, v0, v0
441 ; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s543 ushl v14.4s, v14.4s, v22.4s
544 ushl v15.4s, v15.4s, v22.4s
545 ushl v16.4s, v16.4s, v22.4s
546 ushl v17.4s, v17.4s, v22.4s
655 ushl v2.4s, v25.4s, v24.4s //>>qbit
656 ushl v3.4s, v26.4s, v24.4s //>>qbit
/external/llvm/test/CodeGen/AArch64/
Darm64-vshr.ll37 ; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
/external/libjpeg-turbo/simd/
Djsimd_arm64_neon.S2735 ushl v4.8h, v4.8h, v24.8h /* shift */
2736 ushl v5.8h, v5.8h, v25.8h
2737 ushl v6.8h, v6.8h, v26.8h
2738 ushl v7.8h, v7.8h, v27.8h
3338 ushl v24.8h, v24.8h, v0.8h
3339 ushl v25.8h, v25.8h, v1.8h
3340 ushl v26.8h, v26.8h, v2.8h
3341 ushl v27.8h, v27.8h, v3.8h
3342 ushl v28.8h, v28.8h, v4.8h
3343 ushl v29.8h, v29.8h, v5.8h
[all …]
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc3434 ushl(vf, rd, rn, rm); in VisitNEON3Same()
3467 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in VisitNEON3Same()
3473 ushl(vf, rd, rn, rm).Round(vf); in VisitNEON3Same()
3479 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in VisitNEON3Same()
4668 ushl(vf, rd, rn, rm); in VisitNEONScalar3Same()
4692 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in VisitNEONScalar3Same()
4698 ushl(vf, rd, rn, rm).Round(vf); in VisitNEONScalar3Same()
4704 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in VisitNEONScalar3Same()
Dlogic-aarch64.cc1645 return ushl(vform, dst, src, shiftreg); in shl()
1697 return ushl(vform, dst, extendedreg, shiftreg); in ushll()
1709 return ushl(vform, dst, extendedreg, shiftreg); in ushll2()
1748 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in uqshl()
1796 return ushl(vform, dst, src, shiftreg); in ushr()
1970 LogicVRegister Simulator::ushl(VectorFormat vform, in ushl() function in vixl::aarch64::Simulator
Dsimulator-aarch64.h2224 LogicVRegister ushl(VectorFormat vform,
Dassembler-aarch64.h1741 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
Dmacro-assembler-aarch64.h2241 V(ushl, Ushl) \
Dassembler-aarch64.cc2661 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2074 0x~~~~~~~~~~~~~~~~ 7ef0441f ushl d31, d0, d16
2075 0x~~~~~~~~~~~~~~~~ 6e2244c0 ushl v0.16b, v6.16b, v2.16b
2076 0x~~~~~~~~~~~~~~~~ 6ef24432 ushl v18.2d, v1.2d, v18.2d
2077 0x~~~~~~~~~~~~~~~~ 2ebd44fb ushl v27.2s, v7.2s, v29.2s
2078 0x~~~~~~~~~~~~~~~~ 2e6d45ce ushl v14.4h, v14.4h, v13.4h
2079 0x~~~~~~~~~~~~~~~~ 6ea94496 ushl v22.4s, v4.4s, v9.4s
2080 0x~~~~~~~~~~~~~~~~ 2e3b46d7 ushl v23.8b, v22.8b, v27.8b
2081 0x~~~~~~~~~~~~~~~~ 6e684735 ushl v21.8h, v25.8h, v8.8h
Dlog-disasm2074 0x~~~~~~~~~~~~~~~~ 7ef0441f ushl d31, d0, d16
2075 0x~~~~~~~~~~~~~~~~ 6e2244c0 ushl v0.16b, v6.16b, v2.16b
2076 0x~~~~~~~~~~~~~~~~ 6ef24432 ushl v18.2d, v1.2d, v18.2d
2077 0x~~~~~~~~~~~~~~~~ 2ebd44fb ushl v27.2s, v7.2s, v29.2s
2078 0x~~~~~~~~~~~~~~~~ 2e6d45ce ushl v14.4h, v14.4h, v13.4h
2079 0x~~~~~~~~~~~~~~~~ 6ea94496 ushl v22.4s, v4.4s, v9.4s
2080 0x~~~~~~~~~~~~~~~~ 2e3b46d7 ushl v23.8b, v22.8b, v27.8b
2081 0x~~~~~~~~~~~~~~~~ 6e684735 ushl v21.8h, v25.8h, v8.8h
Dlog-all5451 0x~~~~~~~~~~~~~~~~ 7ef0441f ushl d31, d0, d16
5453 0x~~~~~~~~~~~~~~~~ 6e2244c0 ushl v0.16b, v6.16b, v2.16b
5455 0x~~~~~~~~~~~~~~~~ 6ef24432 ushl v18.2d, v1.2d, v18.2d
5457 0x~~~~~~~~~~~~~~~~ 2ebd44fb ushl v27.2s, v7.2s, v29.2s
5459 0x~~~~~~~~~~~~~~~~ 2e6d45ce ushl v14.4h, v14.4h, v13.4h
5461 0x~~~~~~~~~~~~~~~~ 6ea94496 ushl v22.4s, v4.4s, v9.4s
5463 0x~~~~~~~~~~~~~~~~ 2e3b46d7 ushl v23.8b, v22.8b, v27.8b
5465 0x~~~~~~~~~~~~~~~~ 6e684735 ushl v21.8h, v25.8h, v8.8h
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2417 __ ushl(d31, d0, d16); in GenerateTestSequenceNEON() local
2418 __ ushl(v0.V16B(), v6.V16B(), v2.V16B()); in GenerateTestSequenceNEON() local
2419 __ ushl(v18.V2D(), v1.V2D(), v18.V2D()); in GenerateTestSequenceNEON() local
2420 __ ushl(v27.V2S(), v7.V2S(), v29.V2S()); in GenerateTestSequenceNEON() local
2421 __ ushl(v14.V4H(), v14.V4H(), v13.V4H()); in GenerateTestSequenceNEON() local
2422 __ ushl(v22.V4S(), v4.V4S(), v9.V4S()); in GenerateTestSequenceNEON() local
2423 __ ushl(v23.V8B(), v22.V8B(), v27.V8B()); in GenerateTestSequenceNEON() local
2424 __ ushl(v21.V8H(), v25.V8H(), v8.V8H()); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4120 DEFINE_TEST_NEON_3SAME(ushl, Basic)
4173 DEFINE_TEST_NEON_3SAME_SCALAR_D(ushl, Basic)
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt383 # CHECK: ushl v10.16b, v5.16b, v2.16b
385 # CHECK: ushl v10.8h, v5.8h, v2.8h
387 # CHECK: ushl v10.4s, v5.4s, v2.4s
455 # CHECK: ushl d0, d0, d0
Darm64-advsimd.txt353 # CHECK: ushl.8b v0, v0, v0
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28424 ushl d29, d28, d27 592897214b8152cb2d36d12886b57c9d b18ffa4384c81c2496352c363b3c1e00 b6df9db6e4…
28432 ushl v29.2d, v28.2d, v27.2d 900b8a2887430b297066fc8d5b7145b4 331dd6b4e2c2cc2da898c2c201b4cb1b 0…
28433 ushl v29.4s, v28.4s, v27.4s be4a20d6cfa4f083d41c2bb5d5221b48 7843cc5c9c7d97859e6f8122b160be14 9…
28434 ushl v29.2s, v28.2s, v27.2s cc47b5bcac4507811d8a98279a7b9082 b3d667baa346d921cfec638aa2c3d790 b…
28435 ushl v29.8h, v28.8h, v27.8h bd98ae4ee4797459cec425d5ee514816 e76a0d42b970b933be224cec18b0b944 6…
28436 ushl v29.4h, v28.4h, v27.4h 96d06f003a945b3d6cdeb7b51577e8b7 18932069a44f58f0f027203e57fc08e4 6…
28437 ushl v29.16b, v28.16b, v27.16b 4be504a22638dc8ce90ec373a37a6924 8838c901b766a90dfb4da4f233fbf2a2…
28438 ushl v29.8b, v28.8b, v27.8b 84f41f60057f683a2cea187f41ff7fb7 172d10087f18669728cac652149ab5a8 c…
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md4506 void ushl(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3024 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
3277 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;